HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 209

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
The pin functions that can be selected for pins PA
modes 3 and 4. For the method of selecting the pin functions, see tables 7.12 and 7.13.
The pin functions that can be selected for pins PA
method of selecting the pin functions, see table 7.14.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1 and 2. It is
initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby
mode it retains its previous setting. Therefore, if a transition is made to software standby mode
while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding
pin maintains its output state.
Modes
3 and 4
Modes
1 and 2
Bit
7
DDR is fixed at 1 and PA
Initial value
Read/Write
Initial value
Read/Write
PA DDR
7
⎯
W
7
1
0
PA DDR
7
functions as the A
6
W
W
6
0
0
PA DDR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
20
PA DDR
7
3
address output pin.
to PA
to PA
4
W
W
4
0
0
4
0
Rev.4.00 Aug. 20, 2007 Page 163 of 638
differ between modes 1 and 2, and
are the same in modes 1 to 4. For the
PA DDR
3
W
W
3
0
0
PA DDR
2
W
W
2
0
0
PA DDR
REJ09B0395-0400
1
W
W
1
0
0
7. I/O Ports
PA DDR
0
W
W
0
0
0