HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 156

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
6.2.4
BRCR is an 8-bit readable/writable register that enables address output on bus lines A
enables or disables release of the bus to an external device.
Bit
Modes
1 and 2
Modes
3 and 4
BRCR is initialized to H'FE in modes 1 and 2, and to H'EE in modes 3 and 4, by a reset and in
hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA
0 in this bit enables A
and PA
Bit 7
A23E
0
1
Bit 6—Address 22 Enable (A22E): Enables PA
0 in this bit enables A
and PA
Bit 6
A22E
0
1
Rev.4.00 Aug. 20, 2007 Page 110 of 638
REJ09B0395-0400
4
5
has its ordinary port functions.
has its ordinary port functions.
Initial value
Read/Write
Initial value
Read/Write
Bus Release Control Register (BRCR)
Description
PA
PA
Description
PA
PA
A23E
23
22
R/W
Address 23 to 20 enable
These bits enable PA
used for A
4
4
5
5
⎯
7
1
1
output from PA
output from PA
is the A
is an input/output pin
is the A
is an input/output pin
A22E
23
22
R/W
23
⎯
address output pin
address output pin
6
1
1
to A
20
4
5
. In modes other than 3 and 4, this bit cannot be modified
. In modes other than 3 and 4, this bit cannot be modified
address output
A21E
R/W
⎯
5
1
1
7
to PA
4
5
to be used as the A
to be used as the A
4
A20E
to be
⎯
⎯
4
1
0
⎯
⎯
⎯
3
1
1
Reserved bits
Bus release enable
Enables or disables release
of the bus to an external device
23
22
address output pin. Writing
address output pin. Writing
⎯
⎯
⎯
2
1
1
⎯
⎯
⎯
1
1
1
23
(Initial value)
(Initial value)
to A
BRLE
R/W
R/W
20
0
0
0
and