HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 408
HD6413008VXI25
Manufacturer Part Number
HD6413008VXI25
Description
MCU 3V 0K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13008VFBL25V.pdf
(688 pages)
Specifications of HD6413008VXI25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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12. Serial Communication Interface
Figure 12.8 shows an example of SCI receive operation in asynchronous mode.
12.3.3
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 12.9 shows an example of communication among different processors using a
multiprocessor format.
Rev.4.00 Aug. 20, 2007 Page 362 of 638
REJ09B0395-0400
RDRF
FER
1
Start
bit
Multiprocessor Communication
0
D0
D1
Figure 12.8 Example of SCI Receive Operation
1 frame
Data
(8-Bit Data with Parity and One Stop Bit)
D7
RXI interrupt
Parity
bit
0/1
request
Stop
bit
1
Start
bit
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
0
D0
D1
Data
D7
Parity
bit
0/1
Framing error,
ERI interrupt
request
Stop
bit
Idle (mark) state
1
1
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