HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 384

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12. Serial Communication Interface
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial data can be written in TDR.
Bit 7
TDRE
0
1
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
0
1
Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by
Rev.4.00 Aug. 20, 2007 Page 338 of 638
REJ09B0395-0400
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error will occur and the receive
data will be lost.
Description
TDR contains valid transmit data
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
TDR does not contain valid transmit data
[Setting conditions]
•
•
•
Description
RDR does not contain new receive data
[Clearing conditions]
•
•
RDR contains new receive data
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
The chip is reset or enters standby mode
The TE bit in SCR is cleared to 0
TDR contents are loaded into TSR, so new data can be written in TDR
The chip is reset or enters standby mode
Read RDRF when RDRF = 1, then write 0 in RDRF
(Initial value)
(Initial value)