HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 181

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall
(assertion) of CS
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared to 0, negation of RD in the first read cycle and assertion of CS
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the RD low output in the previous read cycle and the CS
bus cycle will overlap.
As long as RD and CS
non-insertion of an idle cycle can be specified.
Address bus
Data bus
HWR
RD
n
φ
may occur simultaneously. Figure 6.20 shows an example of the operation in
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1)
(a) Idle cycle not inserted
Bus cycle A Bus cycle B
n
T
Long buffer-off time
do not change simultaneously, or if there is no problem even if they do,
1
T
2
T
3
T
1
T
2
Data collision
Address bus
Data bus
Rev.4.00 Aug. 20, 2007 Page 135 of 638
HWR
RD
φ
(b) Idle cycle inserted
Bus cycle A Bus cycle B
T
1
n
n
low output in the following
T
in the following bus cycle
2
T
3
T
REJ09B0395-0400
6. Bus Controller
i
T
1
T
2