AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 102

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

102
AT94KAL Series FPSLIC
Timer/Counter1 useful for lower speed functions or exact-timing functions with infrequent
actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare Regis-
ter 1 A and B – OCR1A and OCR1B as the data sources to be compared to the Timer/Counter1
contents. The Output Compare functions include optional clearing of the counter on compareA
match, and actions on the Output Compare pins on both compare matches.
Timer/Counter1 can also be used as a 8-, 9- or 10-bit Pulse Width Modulator. In this mode, the
counter and the OCR1A/OCR1B registers serve as a dual-glitch-free stand-alone PWM with
centered pulses. Alternatively, the Timer/Counter1 can be configured to operate at twice the
speed in PWM mode, but without centered pulses. Refer to
on this function.
The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 con-
tents to the Input Capture Register – ICR1, triggered by an external event on the Input Capture
Pin – PE7(ICP). The actual capture event settings are defined by the Timer/Counter1 Control
Register – TCCR1B.
Figure 4-32. ICP Pin Schematic Diagram
If the noise canceler function is enabled, the actual trigger condition for the capture event is
monitored over four samples, and all four must be equal to activate the capture flag.
Timer/Counter1 Control Register A – TCCR1A
• Bits 7,6 - COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare
match in Timer/Counter1. Any output pin actions affect pin OC1A – Output CompareA pin PE6.
This is an alternative function to an I/O port, and the corresponding direction control bit must be
set (one) to control an output pin. The control configuration is shown in
• Bits 5,4 - COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0
The COM1B1 and COM1B0 control bits determine any output pin action following a compare
match in Timer/Counter1. Any output pin actions affect pin OC1B – Output CompareB pin PE5.
This is an alternative function to an I/O port, and the corresponding direction control bit must be
set (one) to control an output pin. The following control configuration is given:
Bit
$2F ($4F)
Read/Write
Initial Value
ICPE: Input Capture Pin Enable
7
COM1A1
R/W
0
ICPE
6
COM1A0
R/W
0
5
COM1B1
R/W
0
4
COM1B0
R/W
0
3
FOC1A
R/w
0
page 107
2
FOC1B
R/W
0
for a detailed description
1
PWM11
R/W
0
Table
4-17.
0
PWM10
R/W
0
1138I–FPSLI–1/08
TCCR1A