AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 50

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

50
AT94KAL Series FPSLIC
Figure 4-9.
For single-cycle access (In/Out Commands) to I/O, the instruction has to be less than 16 bits:
In the data SRAM, the registers are located at memory addresses $00 - $1F and the I/O space is
located at memory addresses $20 - $5F.
As there are only 6 bits available to refer to the I/O space, the address is re-mapped down 2 bits.
This means the In/Out commands access $00 to $3F which goes directly to the I/O and maps to
$20 to $5F in SRAM. All other instructions access the I/O space through the $20 - $5F
addressing.
For compatibility with future devices, reserved bits should be written zero if accessed. Reserved
I/O memory addresses should never be written.
The status flags are cleared by writing a logic 1 to them. Note that the CBI and SBI instructions
will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clear-
ing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
$00
$3F
Memory-mapped I/O
opcode
5 bits
Used for In/Out
Instructions
I/O Space
register
r0 - 31 ($1F)
5 bits
Registers r0 - r31
Other Instructions
Memory-mapped
SRAM Space
Used for all
I/O
address
r0 - 63 ($3F)
6 bits
$5F
$1F
$00
1138I–FPSLI–1/08