AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 129

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.29
4.29.1
1138I–FPSLI–1/08
UARTs
Data Transmission
The FPSLIC features two full duplex (separate receive and transmit registers) Universal Asyn-
chronous Receiver and Transmitter (UART). The main features are:
A block schematic of the UART transmitter is shown in
and the functionality is described in general for the two UARTs.
Figure 4-41. UART Transmitter
Note:
• Baud-rate Generator Generates any Baud-rate
• High Baud-rates at Low XTAL Frequencies
• 8 or 9 Bits Data
• Noise Filtering
• Overrun Detection
• Framing Error Detection
• False Start Bit Detection
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed UART Mode
1. n = 0, 1
XTAL
CONTROL LOGIC
GENERATOR
BAUD RATE
STORE UDRn
SHIFT ENABLE
BAUD x 16
IDLE
(1)
UART CONTROL AND
STATUS REGISTER
/16
DATA BUS
BAUD
(UCSRnB)
DATA BUS
AT94KAL Series FPSLIC
REGISTER (UDRn)
SHIFT REGISTER
UART I/O DATA
10(11)-BIT TX
Figure
UART CONTROL AND
TXCn
STATUS REGISTER
IRQ
(UCSRnA)
4-41. The two UARTs are identical
UDREn
IRQ
TXDn
PIN CONTROL
LOGIC
PE0/
PE2
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