AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 39

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 4-2.
1138I–FPSLI–1/08
Mnemonics
STD
ST
ST
ST
STD
LPM
LPM
LPM
IN
OUT
PUSH
POP
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
Instruction Set Summary (Continued)
Operands
Y+q, Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q, Rr
Rd, Z
Rd, Z+
Rd, A
A, Rr
Rr
Rd
Rd
Rd
Rd
Rd
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Description
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Load Program Memory
Load Program Memory and Post-
Increment
In From I/O Location
Out To I/O Location
Push Register on Stack
Pop Register from Stack
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Bit and Bit-test Instructions
Operation
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
Rd ← (Z)
Rd ← (Z), Z ← Z + 1
I/O(A) ← Rr
STACK ← Rr
Rd ← STACK
Rd(0)← C,Rd(n+1)← Rd(n),C← Rd(7)
Rd(7)← C,Rd(n)← Rd(n+1),C← Rd(0)
Rd(n) ← Rd(n+1), n=0..6
SREG(s) ← 1
T ← Rr(b)
Rd(b) ← T
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
S ← 1
S ← 0
R0 ← (Z)
Rd ← I/O(A)
Rd(n+1)← Rd(n),Rd(0)← 0,C← Rd(7)
Rd(n)← Rd(n+1),Rd(7)← 0,C← Rd(0)
Rd(3..0) ↔ Rd(7..4)
SREG(s) ← 0
I/O(A, b) ← 1
I/O(A, b) ← 0
C ← 1
I ← 0
AT94KAL Series FPSLIC
Flags
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V,H
Z,C,N,V
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
#Clock
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
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