AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 151

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 4-30.
1138I–FPSLI–1/08
(TWSR)
Status
Code
$08
$10
$38
$40
$48
$50
$58
A START condition has
been transmitted
A repeated START
condition has been
transmitted
Arbitration lost in
SLA+R or NOT ACK bit
SLA+R has been
transmitted;
ACK has been received
SLA+R has been
transmitted;
NOT ACK has been
received
Data byte has been
received;
ACK has been returned
Data byte has been
received;
NOT ACK has been
returned
Serial Bus and 2-wire
Status of the 2-wire
Status Codes for Master Receiver Mode
Serial Hardware
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
To/From TWDR
Application Software Response
STA
X
X
X
0
1
0
0
1
0
1
0
0
1
0
1
STO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
To TWCR
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AT94KAL Series FPSLIC
TWEA
X
X
X
X
X
X
X
X
0
1
0
1
X
X
X
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
2-wire serial bus will be released and not
addressed Slave mode will be entered
A START condition will be transmitted when
the bus becomes free
Data byte will be received and NOT ACK will
be returned
Data byte will be received and ACK will be
returned
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START
condition will be transmitted and TWSTO flag
will be reset
Data byte will be received and NOT ACK will
be returned
Data byte will be received and ACK will be
returned
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START
condition will be transmitted and TWSTO flag
will be reset
Next Action Taken by 2-wire Serial
Hardware
151