AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 83

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.22.3.2
1138I–FPSLI–1/08
Scanning AVR RESET
When no alternate port function is present, the Input Data - ID corresponds to the PINn register
value, Output Data corresponds to the PORTn register, Output Control corresponds to the Data
Direction (DDn) register, and the PuLL-up Disable (PLD) corresponds to logic expression (DDn
OR NOT(PORTBn)).
Digital alternate port functions are connected outside the dashed box in
scan chain read the actual pin value.
Multiple sources contribute to the internal AVR reset; therefore, the AVR reset pin is not
observed. Instead, the internal AVR reset signal output from the Reset Control Unit is observed,
see
device is in general reset (Resetn or power-on) or configuration download.
Figure 4-22. Observe-only Cell
Figure
RESET CONTROL
4-22. The scanned signal is active High if AVRResetn is Low and enabled or the
UNIT
Previous
From
Cell
ShiftDR
0
1
ClockDR
AT94KAL Series FPSLIC
D
FF1
Q
Next
Cell
To
To System Logic
Figure 4-21
to make the
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