AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 23

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

1138I–FPSLI–1/08
Figure 3-2.
Notes:
$0FFF
$3FFF
$2FFF
$1FFF
$1000
$005F
$0000
$3000
$2000
$001F
1. The Soft “BOOT BLOCK” is an area of memory that is first loaded when the part is powered up
2. The lower portion of the Data memory is not shared between the AVR and FPGA. The AVR
and configured. The remainder of the memory can be reprogrammed while the device is in
operation for switching functions in and out of memory. The Soft “BOOT BLOCK” can only be
programmed by a full device configuration on power-up.
uses addresses $0000 - $001F for the AVR CPU general working registers. $001F - $005F are
the addresses used for Memory Mapped I/O and store the information in dedicated registers.
Therefore, on the FPGA side $0000 - $005F are available for data that is only needed by the
FPGA.
FPSLIC Configurable Allocation SRAM Memory
ACCESS
SRAM
FPGA
DATA
ONLY
Data SRAM Memory
4 Kbytes x 8
4 Kbytes x 8
4 Kbytes x 8
4 Kbytes x 8
OPTIONAL
OPTIONAL
OPTIONAL
FIXED
AVR REG.
MEMORY
MAPPED
during Development
SPACE
AVR
I/O
Memory Partition
is User Defined
(2)
AT94KAL Series FPSLIC
Program SRAM Memory
SOFT “BOOT BLOCK”
4 Kbytes x 16 (94K05)
(1)(2)
2 Kbytes x 16
2 Kbytes x 16
2 Kbytes x 16
OPTIONAL
OPTIONAL
OPTIONAL
10K x 16
FIXED
(1)
$2FFF
$3000
$3FFF
$0000
$07FF
$27FF
$2800
$37FF
$3800
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