AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 58

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

58
AT94KAL Series FPSLIC
Figure 4-10. Out Instruction – AVR Writing to the FPGA
Note:
Figure 4-11. In Instruction – AVR Reading FPGA
Notes:
(FPGA DATA OUT)
(FISUA, B, C or D)
AVR CLOCK
(FISUA, B, C or D)
SYSTEM CLOCK)
AVR IOADR
FPGA IORE
SELECT "n"
FPGA CLOCK
1. AVR expects Write to be captured by the FPGA upon posedge of the AVR clock.
1. AVR captures read data upon posedge of the AVR clock.
2. At the end of an FPGA read cycle, there is a chance for the AVR data bus contention between
AVR DBUS
(FPGA DATA IN)
AVR IORE
AVR CLOCK
FPGA IOWE
AVR INST
AVR IOADR
SELECT "n"
FPGA I/O
AVR DBUS
the FPGA and another peripheral to start to drive (active IORE at new address versus
FPGAIORE + Select “n”), but since the AVR clock would have already captured the data from
AVR DBUS (= FPGA Data Out), this is a “don’t care” situation.
AVR IOWE
(SET TO AVR
AVR INST
FPGA I/O
OUT INSTRUCTION
IN INSTRUCTION
WRITE DATA VALID
READ DATA VALID
(1)
(2)
(2)
(1)
1138I–FPSLI–1/08