AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 162

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.31.2.3
4.31.2.4
162
AT94KAL Series FPSLIC
Alternate I/O Functions of PortE
PortE Schematics
immediately tri-state. This function happens only if the Check pin has been enabled in the sys-
tem control register. The use of the Check pin will NOT disable the use of that pin as an input to
PE7 nor as an input as alternate INT3.
PortE may also be used for various Timer/Counter functions, such as External Input Clocks
(TC0 and TC1), Input Capture (TC1), Pulse Width Modulation (TC0, TC1 and TC2), and toggling
upon an Output Compare (TC0, TC1 and TC2). For a detailed pinout description, consult
4-35 on page
page 89.
Note that all port pins are synchronized. The synchronization latches are, however, not shown in
the figures.
Figure 4-53. PortE Schematic Diagram (Pin PE0)
PE0
TX0
PULL-UP
PULL-UP
MOS
MOS
160. For more information on the function of each pin,
RESET
DL
RESET
TX0D
DL
GTS
GTS
RP
0
1
DL
DL
T0
TX0D
TX0ENABLE
SCR(52)
TX0ENABLE
SCR(52)
GTS: Global Tri-state
DL: Configuration Download
WL: Write PORTE
WD: Write DDRE
RL: Read PORTE Latch
RD: Read DDRE
RP: Read PORTE Pin
TX0D: UART 0 Transmit Data
TX0ENABLE: UART 0 Transmit Enable
SCR: System Control Register
T0: Timer/Counter0 Clock
See “Timer/Counters” on
Q
Q
PORTE0
RESET
RESET
DDE0
WD
WL
RD
RL
R
R
D
D
1138I–FPSLI–1/08
Table