AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 33

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

1138I–FPSLI–1/08
Table 3-7.
Bit
SCR54
SCR55
SCR56
SCR57
SCR58 - SCR59
SCR60 - SCR61
SCR62
SCR63
FPSLIC System Control Register (Continued)
Description
0 = AVR Port D I/O With 6 mA Drive
1 = AVR Port D I/O With 20 mA Drive
0 = AVR Port E I/O With 6 mA Drive
1 = AVR Port E I/O With 20 mA Drive
0 = Disable XTAL Pin (R
1 = Enable XTAL Pin (R
0 = Disable TOSC2 Pin (R
1 = Enable TOSC2 Pin (R
Reserved
SCR61 = 0, SCR60 = 0 “1”
SCR61 = 0, SCR60 = 1 AVR System Clock
SCR61 = 1, SCR60 = 0 Timer Oscillator Clock (TOSC1)
SCR61 = 1, SCR60 = 1 Watchdog Clock
Global Clock 6 mux select (set by using the AT94K Device Options in System
Designer).
Note:
0 = Disable CacheLogic Writes to FPGA by AVR
1 = Enable CacheLogic Writes to FPGA by AVR
0 = Disable Access (Read and Write) to SRAM by FPGA
1 = Enable Access (Read and Write) to SRAM by FPGA
1. The AS2 bit must be set in the ASSR register.
feedback
feedback
feedback
feedback
)
)
)
)
AT94KAL Series FPSLIC
(1)
33