AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 56

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

56
AT94KAL Series FPSLIC
Table 4-4.
Note:
In summary, 16 select signals are sent to the FPGA for I/O addressing. These signals are
decoded from four base I/O Register addresses (FISUA..D) and extended to 16 with two bits
from the FPGA I/O Select Control Register, XFIS1 and XFIS0. The FPGA I/O read and write sig-
nals, FPGAIORE and FPGAIOWE, are qualified versions of the AVR IORE and IOWE signals.
Each will only be active if one of the four base I/O addresses is accessed.
Reset: all select lines become active and an FPGAIOWE strobe is enabled. This is to allow the
FPGA design to load zeros (8’h00) from the D-bus into appropriate registers.
Read or Write
I/O Address
FISUA $14 ($34)
FISUB $15 ($35)
FISUC $16 ($36)
FISUD $17 ($37)
1. Not available on AT94K05.
FPGA I/O Select Line Scheme
(1)
(1)
XFIS1
FISCR Register
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
XFIS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
15..12
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
FPGA I/O Select Lines
11..8
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
7..4
1138I–FPSLI–1/08
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
3..0