AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 159

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.31.2
1138I–FPSLI–1/08
PortE
Table 4-34.
Note:
Figure 4-52. PortD Schematic Diagram
PortE is an 8-bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for the PortE, one each for the Data Register
– PORTE, $07($27), Data Direction Register – DDRE, $06($26) and the PortE Input Pins –
PINE, $05($25). The PortE Input Pins address is read only, while the Data Register and the
Data Direction Register are read/write.
The PortE output buffers can sink 20 mA. As inputs, PortE pins that are externally pulled Low
will source current if the pull-up resistors are activated.
All PortE pins have alternate functions as shown in
DDDn
0
0
1
1
(1)
1. n: 7,6...0, pin number
PD*
PULLUP
MOS
DDDn
PORTDn
0
1
0
1
(1)
Bits on PortD Pins
(1)
Output
Output
Input
Input
I/O
RESET
DL
GTS
Pull-up
RP
DL
Yes
No
No
No
AT94KAL Series FPSLIC
Table
Comment
Tri-state (High-Z)
PDn will source current if
external pulled low (default)
Push-pull zero output
Push-pull one output
4-35.
GTS: Global Tri-State
DL: Configuration Download
WL: Write PORTD
WD: Write DDRD
RL: Read PORTD Latch
RD: Read DDRD
RP: Read PORTD Pin
Q
Q
PORTD*
RESET
RESET
DDD*
WD
WL
RD
RL
R
R
D
D
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