AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 111

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

1138I–FPSLI–1/08
Watchdog Timer Control Register – WDTCR
• Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the FPSLIC and will always read as zero.
• Bit 4 - WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be dis-
abled. Once set, the hardware will clear this bit to zero after four clock cycles. Refer to the
description of the WDE bit below for a watchdog disable procedure.
• Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, but if the WDE is cleared (zero), the
Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To
disable an enabled Watchdog Timer, the following procedure must be followed:
• Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Time-out periods
are shown in
Table 4-23.
Note:
Bit
$21 ($41)
Read/Write
Initial Value
WDP2
1. In the same operation, write a logic 1 to WDTOE and WDE. A logic 1 must be written
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the watchdog.
0
0
0
0
1
1
1
1
to WDE even though it is set to one before the disable operation starts.
1. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Char-
acteristics section. The WDR (watchdog reset) instruction should always be executed before
the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with
the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start counting from zero.
Table
Watchdog Timer Prescale Select
7
-
R
0
WDP1
0
0
1
1
0
0
1
1
4-23.
6
-
R
0
WDP0
0
1
0
1
0
1
0
1
5
-
0
R
4
WDTOE
R/W
0
Oscillator Cycles
Number of WDT
AT94KAL Series FPSLIC
1,024K
2,048K
128K
256K
512K
16K
32K
64K
3
WDE
R/W
0
(1)
2
WDP2
R/W
0
1
WDP1
R/W
0
Typical Time-out
at V
15 ms
30 ms
60 ms
0
WDP0
R/W
0
0.12s
0.24s
0.49s
0.97s
CC
1.9s
= 3.0V
WDTCR
111