AT94K05AL-25AJI Atmel, AT94K05AL-25AJI Datasheet - Page 43

• Manufacturer Part Number: AT94K05AL-25AJI
• Description: IC FPSLIC 5K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.5
1138I–FPSLI–1/08
Architectural Overview
The AVR uses a Harvard architecture concept – with separate memories and buses for program
and data. The program memory is accessed with a single level pipeline. While one instruction is
being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock-cycle. The program memory is in-system pro-
grammable SRAM memory. With a few exceptions, AVR instructions have a single 16-bit word
format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the
stack. The stack is effectively allocated in the general data SRAM, as a consequence, the stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the Stack Pointer (SP) in the reset routine (before subroutines or interrupts are exe-
cuted). The 16-bit stack pointer is read/write accessible in the I/O space.
The data SRAM can be easily accessed through the five different addressing modes supported
in the AVR architecture.
A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the status register. All the different interrupts have a separate interrupt
vector in the interrupt vector table at the beginning of the program memory. The different inter-
rupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The memory spaces in the AVR architecture are all linear and regular memory maps.
AT94KAL Series FPSLIC
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