TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 113

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

15. DMACC0Control (DMAC Channel0 Control Register)
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23:21]
[20:18]
[17:15]
[14:12]
[11:0]
Bit
I
Prot[3]
Prot[2]
Prot[1]
DI
SI
D
S
Dwidth[2:0]
Swidth[2:0]
DBSize[2:0]
SBSize[2:0]
TransferSize
Symbol
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
TMPA901CM- 112
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y000
0y000
0y000
0y000
0x000
Reset
Value
Terminal count interrupt enable register when using the
scatter/gather function
0y0: Disable
0y1: Enable
Control cache permission HPROT[3]
0y0: Noncacheable
0y1: Cacheable
Control buffer permission HPROT[2]
0y0: Nonbufferable
0y1: Bufferable
Control privileged mode HPROT[1]
0y0: User mode
0y1: Privileged mode
Increment the transfer destination address
0y0: Do not increment
0y1: Increment
Increment the transfer source address
0y0: Do not increment
0y1: Increment
Transfer destination AHB Master
0y0: DMA1
0y1: DMA2
Transfer source AHB Master
0y0: DMA1
0y1: DMA2
Transfer destination bit width
0y000: Byte (8 bits)
0y001: Half-word (16 bits)
0y010: Word (32 bits)
other: Reserved
Transfer source bit width
0y000: Byte (8 bits)
0y001: Half-word (16 bits)
0y010: Word (32 bits)
other: Reserved
Transfer destination burst size:
0y000 1 beat
0y001 4 beats
0y010: 8 beats
0y011: 16 beats
0y100: 32 beats
0y101: 64 beats
0y110: 128 beats
0y111: 256 beats
Transfer source burst size:
0y000: 1 beat
0y001: 4 beats
0y010: 8 beats
0y011: 16 beats
0y100: 32 beats
0y101: 64 beats
0y110: 128 beats
0y111: 256 beats
Set the total transfer count
Address
Description
(0xF410_0000) + (0x010C)
TMPA901CM
2010-07-29