TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 601

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.17.5
i2sr_act
i2st_act
finish_DMA
i2s_stop_t
i2s_stop_r
Setting example of Transmission master and Receive slave
Setting example
I2SCOMMON
I2STCON
I2SRCON
I2SRMS
GPIOMFR1
GPIOLFR1
0xf8004000
．．．
0xf800403c
0xf8004040
0xf8004044
0xf8004048
0xf800404c
．．．
DMACConfiguration
DMACC0SrcAddr
DMACC0DestAddr
DMACC0Control
DMACC0Configuration
I2SRSLVON
I2SRST
LDR
AND
LDR
CMP
BNE
I2SRDMA1
DMACConfiguration
DMACC1SrcAddr
DMACC1DestAddr
DMACC1Control
DMACC1Configuration
I2STSLVON
I2SRST
LDR
AND
LDR
CMP
BNE
I2STDMA1
DMACC0Control
CMP
I2STDMA1
I2SRDMA1
I2STSLVON
I2SRSLVON
I2STST
LDR
AND
LDR
CMP
BNE
I2SRST
LDR
I2STFCLR
I2SFRFCLR
BNE
AND
LDR
CMP
BNE
r1, = 0xc
r0,#0x0
r1, = 0x0
finish_DMA
i2s_stop_r
r0,r0,r1
r0,r1
i2sr_act
i2st_act
r1, = 0xc
r0,r0,r1
r2, = 0xc
r0,r2
r1, = 0xc
r0,r0,r1
r2, = 0xc
r0,r2
r1, = 0xc
r0,r0,r1
r1, = 0x0
r0,r1
i2s_stop_t
TMPA901CM- 600
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
→
←
←
←
←
←
←
←
→
←
→
←
←
←
←
→
→
←
←
0x00000001
0x00000000
0x00000000
0x00000000
0x000000FF
0x000000FF
0x0000FFFF
．．．
0xFFFF0000
0xf8004020
I2STDAT
0xf8004050
0x04492008
．．．
0x00000001
I2SRDAT
0xf8008000
0x08492008
0x00001017
0x00000001
r0
0x00000001
0x00000001
0xf8004000
I2STDAT
0x04492008
0x00000a81
0x00000001
r0
0x00000001
r0
0x00000000
0x00000000
0x00000000
0x00000000
r0
r0
0x00000001
0x00000001
; write 0x00000001 to Register
; Rx is slave
; Set transfer data
; End of set data
; Use DMA scatter gather link
; source address
; destination address
; next address
; Set DMAC control register
; Set Rx DMAC
; I2S internal clock on
; label i2sr_act
; read I2SRST register data to r0
; check I2S Active
; r0 ≠r2 ,
;I2S DMA Ready
; Set Tx DMAC
; I2S internal clock on
; label i2st_act
; read I2SRST register data to r0
; check I2S Active
; r0 ≠r2 ,
;I2S DMA Ready
; label
; read DMACC0Control data to r0
; check the End of Rx DMAC
; r0 ≠0x0 , jump to finish_DMA
; DMA Clear
; internal clock off
; label
; read I2STST register data to r0
; check I2S Tx standby
; label
; read I2SRST register data to r0
; check I2S Rx standby
; r0 ≠r1 ,
; clear Tx FIFO
; clear Rx FIFO
jump to i2sr_act
jump to i2st_act
jump to i2st_stop_r
TMPA901CM
2010-07-29