TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 605
TMPA901CMXBG
Manufacturer Part Number
TMPA901CMXBG
Description
Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
Manufacturer
Toshiba
Datasheet
1.TMPA901CMXBG.pdf
(858 pages)
Specifications of TMPA901CMXBG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
-
Rom Type
ROMless
Ram (kbytes)
32
Number Of Pins
177
Package
BGA
Vcc
3V
Tft Lcd Controller
Y
Touchscreen Controller
Y
Usb Host Fs With Phy
Y
Usb Device Hs With Phy
Y
Sd Host Controller
-
Cmos Image Sensor Interface
-
I2s
1
Ssp (ch) Spi
1
I2mc/sio (ch)
1
Uart/sio (ch)
2
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
8
10-bit Ad Converter
4
12-bit Da Converter
-
16-bit Timer / Counter
6
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
Y
Low-power Modes
Y
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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bpp
bpp
16
24
16
24
1
2
4
8
1
2
4
8
P31
P15
31
15
15
15
15
0
1
3
7
0
1
3
7
3.18.2.2
P15
P7
P30
P14
30
14
14
14
14
0
0
2
6
0
0
2
6
P7
P3
converts it into 24-, 16-, 8-, 4-, 2-, or 1-bit data according to the operation mode.
the lower DMA FIFO (16 words) and read alternately.
RAM or output directly without bypassing the palette.
Pixel Serializer
P29
P13
29
13
13
13
13
This block reads LCD data of 32-bit width from the DMA FIFO's output port and
In the dual panel mode, data is divided into the higher DMA FIFO (16 words) and
Data converted into a suitable size is used as color/gray level values in the palette
0
1
1
5
0
1
1
5
P14
P6
P28
P12
28
12
12
12
12
0
0
0
4
0
0
0
4
Table 3.18.2 LBLP: DMA FIFO output bits 31 to 16
Table3.18.3 LBLP: DMA FIFO output bits 15 to 0
P1
P3
P27
P11
27
11
11
11
11
0
1
3
3
0
1
3
3
P13
P5
P26
P10
26
10
10
10
10
0
0
2
2
0
0
2
2
TMPA901CM- 604
P2
P6
DMA FIFO output bit
P25
25
P9
9
0
1
1
1
9
9
0
1
1
1
9
DMA FIFO output bit
P4
P12
P8
P24
8
0
0
0
0
8
8
24
P0
P0
0
0
0
0
8
P1
P0
P7
7
0
1
3
7
7
7
P23
23
23
0
1
3
7
7
P3
P11
P6
6
0
0
2
6
6
6
P22
22
22
0
0
2
6
6
P1
P5
P5
5
0
1
1
5
5
5
P21
21
21
P2
0
1
1
5
5
P10
P4
4
0
0
0
4
4
4
P0
P20
20
20
0
0
0
4
4
P3
3
0
1
3
3
3
3
P2
P1
P19
19
19
0
1
3
3
3
P2
2
0
0
2
2
2
2
TMPA901CM
P9
P0
2010-07-29
P18
18
18
0
0
2
2
2
P1
1
0
1
1
1
1
1
P4
P0
P17
17
17
P0
0
1
1
1
1
0
0
0
0
0
0
0
P8
P16
16
16
0
0
0
0
0
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