TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 96

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.8.2
DMA Request Number
UART0 transmit [0]
UART0 transmit [0]
SSP0 transmit [2]
SSP0 transmit [2]
UART0 receive [1]
UART0 receive [1]
SSP0 receive [3]
SSP0 receive [3]
Block Diagram
Reserved [13]
Reserved [12]
Reserved
Reserved
Reserved [13]
Reserved [12]
Reserved [9]
Reserved [8]
Reserved [7]
Reserved [6]
Reserved [5]
LCDDA [14]
NANDC [4]
LCDDA [14]
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
I2S1 [10]
I2S0 [11]
[15]
[10]
[15]
[11]
[9]
[8]
[7]
[6]
[5]
[4]
burst request
CPU Data.
Table 3.8.2 DMA request number chart
request
Single
UART0 transmit
UART0 receive
SSP0 transmit
SSP0 receive
NANDC
Reserved
Reserved
Reserved
Reserved
Reserved
I2S1
I2S0
Reserved
Reserved
LCDDA
TMPA901CM- 95
response
request
DMA
slave
and
AHB
I/F
I/F
Burst
Channel
register
register
Peripheral
Control
logic
logic
and
and
UART0 transmit
UART0 receive
SSP0 transmit
SSP0 receive
Reserved
Reserved
Reserved
Reserved
LCDDA
Interrupt
request
master
master
AHB
AHB
I/F 1
I/F 2
Single
DMA1
(DMACINTERR)
INTS [17]
(DMACINTTC)
DMACCLR[15:0]
INTS [16]
DMA2
TMPA901CM
2010-07-29