TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 491

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.2.11 USB Bus Power Detecting Sequence
(1) Connect
the bus power from the USB host (VBUS), initialize UDC2AB and UDC2 with the
following procedures:
(2) Disconnect
external interrupt. Since master transfers will not automatically stop in such
circumstances, you need to make an abort process. Then use the pw_resetb bit of Power
Detect Control register to make software reset.
suspended, no interrupt will be notified even if the power is disconnected while CLK_H
is stopped. In such cases, resuming of CLK_H is required using the WAKEUP_X
output signal. See section 3.16.2.13 “(4) Signal operations when suspended and
resumed (disconnected)" for more information.
1. Use the pw_resetb bit of Power Detect Control register to make software reset.
2. Make an access to UDC2AB and UDC2 registers to make necessary initial
3. Use UDC2 Command register to issue the USB Ready command. UDC2 notifies
4. Once USB_RESET from the USB host is detected, UDC2 initializes the registers
This section describes the sequence when detecting the power supply. After detecting
When the USB bus power is disconnected, UDC2AB makes notification by an
In case the system employs the control to stop CLK_H (AHB end) while USB is
(The pw_resetb bit is not automatically released and should be cleared by
software.)
settings.
the USB host of the connection via PHY. This condition enables UDC2 to accept
USB_RESET from the USB host.
inside UDC2 and enumeration with the USB host becomes available. When
USB_RESET is detected, the int_usb_reset/int_usb_reset_end interrupt occurs.
Note: While UDC2AB originally has the function to assert the int_powerdetect interrupt when
VBUS is detected, it is not supported for this LSI. UDPWCTL<pw_detect> always indicates
0.
TMPA901CM- 490
TMPA901CM
2010-07-29