TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 409

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[Notes on Specifications]
Other register bits
3.14.6.15 Register Values after a Software Reset
Software reset
<When a software reset releases SCL (0→1) while SDA = 1 >
<I2CM>
<LRB>
circuitry and releases the SCL and SDA lines. (Refer to Section 3.14.6.3 “(2) Clock
synchronization”.)
return a value other than the initial value (0).
SDA
A software reset initializes the I
However, depending on read timing after a software reset, reading I2C0SR<LRB> may
SCL
Initialized by a software reset
TMPA901CM- 408
↑
2
C registers other than I2C0CR2<I2CM> and internal
<LRB> = 0 (initial value)
on read
is recognized and <LRB> is set to 1.
After SCL is released, rising
<LRB> =1 on
↑
read
TMPA901CM
2010-07-29