TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 377

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

I2C0SR
<TRX>
interrupt request
I2C0SR<PIN>
1
0
I2CINT0
Table 3.14.1 I2CINT0 interrupt request and I2C0SR<PIN> operations after arbitration lost
Note: In slave mode, if I2C0AR<SA> is set to 0x00 and a START byte (0x01) of the I
I2C0SR
<AL>
1
0
1
0
slave address match is detected and I2C0SR<TRX> is set to 1. Do not set I2C0AR<SA> to 0x00.
is pulled low. Either writing data to I2C0DBR or setting I2C0CR2<PIN> to 1 releases
I2C0CL after the t
implement required operations, as shown in Table 3.14.2.
When an I2CINT0 interrupt request occurs, I2C0SR<PIN> is reset to 0, and I2C0CL
Check I2C0SR<AL>, I2C0SR<TRX>, I2C0SR<AAS> and I2C0SR<AD0>, and
transmission of slave address as master
An I2CINT0 interrupt request is generated after the current word of data has been transferred.
I2C0SR
<AAS>
When arbitration lost occurs during
1
1
0
1
0
1
0
I2C0SR
<AD0>
1/0
1/0
1/0
0
0
0
0
Table 3.14.2 Operations in slave mode
LOW
address transmission, and receives a
slave address with direction bit set to 1
from another master.
completes the transmission of 1-word
data.
The device loses arbitration during slave
In slave receiver mode, the device
receives a slave address with direction
bit set to 1 from the master.
In slave transmitter mode, the device
The device loses arbitration during slave
address transmission, and receives a
slave address with direction bit set to 0
from another master or receives a
general call.
The device loses arbitration when
transmitting a slave address or data, and
completes transferring the current word
of data.
In slave receiver mode, the device
receives a slave address with direction
bit set to 0 from another master or
receives a general call.
In slave receiver mode, the device
completes the receipt of 1-word data.
period.
TMPA901CM- 376
I2C0SR<PIN> is cleared to 0.
Condition
When arbitration lost occurs during transmission of
data as master transmitter
Set the number of bits in 1 word to
I2C0CR1<BC> and write the data to be
transmitted to I2C0DBR.
Check I2C0SR<LRB>. If it is set to 1,
the receiver is not requesting the next
data, so set I2C0CR2<PIN> to 1. Then,
clear I2C0CR2<TRX> to 0 to release
the bus.
If I2C0SR<LRB> = 0, the receiver is
requesting the next data, so set the
number of bits in 1 word in
I2C0CR1<BC> and write the data to be
transmitted to I2C0DBR.
Write dummy data (0x00) to I2C0DBR to
set I2C0SR<PIN> to 1, or write 1 to
I2C0CR2<PIN>.
The device is set as a slave. Clear
I2C0SR<AL> to 0 and write dummy
data (0x00) to I2C0DBR to set
I2C0SR<PIN> to 1.
Write dummy data (0x00) to I2C0DBR to
set I2C0SR<PIN> to 1, or write 1 to
I2C0CR2<PIN>.
Set the number of bits in 1 word to
I2C0CR1<BC>, read the received data
from I2C0DBR and write dummy data
(0x00).
2
C bus standard is received, a
Operation
TMPA901CM
2010-07-29