TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 397

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.14.6.3 Serial Clock
I2CxCL signal
Note: The t
the low level period must be 5/Tprsck [s] or longer for externally input serial clocks,
regardless of the I2C0CR1<SCK> setting.
when a stop condition is generated are defined as t
defined as t
(1) Clock source
master mode.
I2C0CR1<SCK> is used to set the high and low periods of the serial clock to be output in
In master mode, the hold time when a start condition is generated and the setup time
When I2C0CR2<PIN> is set to 1 in slave mode, the time to the release of I2C0CL is
In both master and slave modes, the high level period must be 4/Tprsck [s] or longer and
t
t
fscl
HIGH
LOW
combination of bus load capacitance and pull-up resistor. If the clock synchronization function for
synchronizing clocks from multiple clocks is used, the actual clock period may differ from the specified setting.
1/(t
HIGH
(j/Tprsck)
t
t
(i/Tprsck)
HIGH
LOW
HIGH
LOW
period may differ from the specified value if the rising edge becomes blunt depending on the
>
>
[s].
t
LOW
(5/Tprsck)
(4/Tprsck)
0y000
0y001
0y010
0y011
0y100
0y101
0y110
0y111
SCK
t
HIGH
)
Figure 3.14.12 I2CxCL output
Figure 3.14.13 SCLK input
t
HIGH
t
LOW
t
TMPA901CM- 396
HIGH
(i / Tprsck)
134
262
10
14
22
38
70
8
i
1/fscl
t
LOW
t
LOW
(j / Tprsck)
138
266
HIGH
12
14
18
26
42
74
j
[s].
TMPA901CM
2010-07-29