TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 625

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:5]
[4]
[3]
[2]
[1]
[0]
[31:5]
[4]
[3]
[2]
[1]
[0]
Bit
Bit
10. LCDMIS (Masked Interrupt Status Register)
11. LCDICR (Interrupt Clear Register)
LCDRIS register and the LCDIMSC (Enable) register. The logical ORs of all interrupts are
given to the system interrupt controller.
LCDMIS is a read-only register. This register serves as the logical AND for each bit of the
MBERRORINTR
VCOMPINTR
LNBUINTR
FUFINTR
Clear
MBERROR
Clear Vcomp
Clear LNBU
Clear FUF
Symbol
Symbol
Bit
Bit
Type
RO
RO
RO
RO
Type
WO
WO
WO
WO
Undefined
0y0
0y0
0y0
0y0
Undefined
Undefined
0y0
0y0
0y0
0y0
Undefined
Reset
Value
TMPA901CM- 624
Reset
Value
Read as undefined. Write as zero.
Clears AMBA AHB master bus error interrupt request flags
0y0: No change
0y1: Clear
Clears vertical sync. interrupt request flags.
0y0: No change
0y1: Clear
Clears LCD next address base update interrupt request flags.
0y0: No change
0y1: Clear
Clears FIFO underflow interrupt request flags.
0y0: No change
0y1: Clear
Read as undefined. Write as zero.
Read as undefined. Write as zero.
AMBA AHB master bus error status bit
0y0: Clear
0y1: Interrupt requested
Vertical sync. interrupt status bit
0y0: Clear
0y1: Interrupt requested
LCD next address base update status bit
0y0: Clear
0y1: Interrupt requested
FIFO underflow status bit
0y0: Clear
0y1: Interrupt requested
Read as undefined.
Address
Description
Description
Address
(0xF420_0000) + (0x0024)
(0xF420_0000) + (0x0028)
TMPA901CM
2010-07-29