TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 540

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.3.4 USB Device Response
hardware reset, UDC2 initializes internal registers and all endpoints are in the invalid
status, which means the device itself is “Disconnected.”
Issuing this command will put UDC2 in the "Full-Speed" mode, enable the Pull-Up
resistance of DDP and notify the host of “Connect.”
USB signal, putting the device in the “Default” status. In this status only Endpoint 0
gets “Ready” enabling enumeration with the host.
When Chirp from the host is normally received, the mode of UDC2 turns to High-Speed
(HS) and subsequent transfers between the hosts will be made in the HS mode. If
Chirp from the host is not received, subsequent transfers between the hosts will be
made in the Full-Speed (FS) mode.
register.
Address-state register after receiving the “Set_address” request, UDC2 will be in the
“Addressed” status. Setting for this register should be made after the Control transfer
has successfully finished (after the STATUS-Stage has ended).
(1) When hardware reset is detected
(2) When USB_RESET is detected
(3) When “Set_address” request is received
is detected, USB_RESET is detected, and an enumeration response is made. This
section discusses the operations of UDC2 in each status as well as how to control them
externally.
Be sure to reset hardware for UDC2 after the power-on operation. After the
In order to make the status of UDC2 to “Default,” issue the “USB_Ready”" command.
In this status, only the USB_RESET signal is accepted from the host.
UDC2 initializes internal registers when Bus Reset (USB_RESET) is detected on the
The mode of UDC2 will be “HS-Chirp” and Chirp operation with the host will start.
The current transfer mode can be judged by reading the bits[13:12] of Address-state
By setting 0y010 to the bits[10:8] and the received address value to the bits[6:0] of
Transfers to endpoints other than Endpoint 0 cannot be made in this status.
UDC2 initializes the inside of UDC2 and sets various registers when hardware reset
TMPA901CM- 539
TMPA901CM
2010-07-29