TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 615

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

b. <CPL>
c.
d. <IPC>
e. <IHS>
f.
This value is obtained by dividing the number of pixels per line by 1, 4, 8 or 8/3, and then
subtracting one from the quotient. To allow the LCD controller to function properly, this
field needs to be programmed properly in addition to PLL.
display data is available. It can be used only for TFT displays.
TFT
STN
<IOE>
This bit set the panel clock edge.
This bit set the polarity of Horizontal sync signal.
<IVS>
This bit set the polarity of Vertical sync signal.
The IOE bit specifies the polarity of the data enable signal.
The CPL field specifies the actual number of LCLCP clocks per line in the LCD panel.
The data enable signal is output on the LCLAC pin to notify the LCD panel when valid
Panel Type
Monochrome
Color
Bus Width
－
4
8
8
TMPA901CM- 614
Note: Round up all digits to the right
CPL =
CPL =
CPL =
CPL =
of the decimal point.
(Number of pixels per line)
(Number of pixels per line)
(Number of pixels per line)
(Number of pixels per line)
CPL Calculation Formula
1
4
8
8
3
－1
－1
－1
－1
TMPA901CM
2010-07-29