TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 383

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

c. <NOACK>
d. <SCK[2:0]>
Writes to this register must be done before a start condition is generated or after a stop condition is generated or
between the instant when an address or data transfer interrupt occurs and the instant when the internal interrupt is
released. Do not write to this register during address or data transfer.
Note: Refer to Section 3.14.5 6. I2C0PRS (I2C0 Prescaler Clock Set Register)” and Section 3.14.6.3 “Serial Clock”.
general call detection when this module is a slave.
enabled. When a slave address match or general call is detected, the slave pulls the SDA
line low during the 9th (acknowledge) clock output from the master to return an
acknowledge signal.
detection. When a slave address match or general call is detected, the slave releases (holds
high) the SDA line during the 9th (acknowledge) clock output from the master to return no
acknowledge signal.
clock for serial clock generation. The prescaler clock is further divided according to
I2C0CR1<SCK[2:0]> to generate the serial clock. The default setting of the prescaler clock
is “divide by 1” ( f
This bit specifies whether to enable or disable the slave address match detection and
0y0: Enable
0y1: Disable
When I2C0AR<ALS>
When <NOACK>
Setting <NOACK>
These bits are used to set the rate of serial clock to be output from the master.
The prescaler clock divided according to I2C0PRS<PRSCK[4:0]> is used as the reference
PCLK
0, the slave address match detection and general call detection are
).
1 disables the slave address match detection and general call
1, this bit has no meaning.
TMPA901CM- 382
TMPA901CM
2010-07-29