TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 42

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

0xFFFF_FFFF
0xF0A0_0000
0xF800_A000
0x0000_0000
0x0000_2000
0x0000_4000
0x0100_0000
0x2000_0000
0x2100_0000
0x4000_0000
0x6000_0000
0x8000_0000
0xF000_0000
0xF010_0000
0xF080_0000 Internal IO-1 (APB Port1/2) : 1MB
0xF090_0000 Internal IO-2 (APB Port2/2) : 1MB
0xF200_0000 Internal IO-3 (AHB+APB) : 16MB
0xF300_0000
0xF400_0000
0xF600_0000
0xF800_0000
0xF800_2000
0xF800_4000
0xF800_8000
Address
Figure 3.3.2 Memory map (details of start mode and Bus Master and Slave connection)
Note: USB Host can access the area of 0xF800_8000 to 0xF800_9FFF only.
Dual port RAM share with LCDDA
Activation of the internal
Internal RAM-3 : 8KB(Remap)
Internal IO-4 (AHB) : 16MB
Internal ROM : 8KB+ 8KB
Internal IO-0 (APB) : 1MB
Internal RAM-0 : 16KB
share with USB Host
Internal RAM-1 : 8KB
BOOT ROM
Unused area
Unused area
Unused area
Unused area
Unused area
Unused area
Unused area
Unused area
SMCCS0n
SMCCS0n
SMCCS1n
DMCCSn
External area (1792MB)
External area (15.8MB)
External area (512MB)
External area (496MB)
External area (512MB)
External area (512MB)
Remap area (8KB)
Internal I/O area
Internal memory
TMPA901CM- 41
area(128MB)
(128MB)
CPU(D) CPU(I) LCDC LCDDA DMA1 DMA2
M1
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○ : Access available,× : Access unavailable
M2
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Bus Master and Slave connection
Please refer to next page.
M3
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－ : Don’t access
M4
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M5
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TMPA901CM
2010-07-29
M6
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USB
M7
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