TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 665

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31]
[30]
[29:19]
[18:6]
[5:3]
[2:0]
[Description]
a. <OVWEN>
b. <INDSAEN>
Bit
6. LDADVSRC0 (LCDDA Delta Value (Read Step) address Register of Source 0)
LCD Panel
TMPA901
image processed on the LCDDA. Setting 1 uses the front address setting of the destination
image into the front address of Source 0 image too. In circuitry, the blend is executed and
used to change the display which is blended part of current displaying image.
LCDC
This bit is used when increment steps differ between Source 0 image and Source 1 image
in an image processed for BLEND on the LCDDA. Setting 1 can set the number of steps
individually for each Source 0 image and Source 1 image.
When 0 is set, the increment step set for Source 1 image is used for the increment step in
Source 0 image.
This bit is used when Source 0 image and the destination image are the same in an
OVWEN
INDSAEN
DYS0[12:0]
DXS0[2:0]
Symbol
Blending
LCDDA
Bit
RW
RW
R/W
R/W
Type
READ
WRITE
READ
0y0
0y0
Undefined
0x000
Undefined
0y000
TMPA901CM- 664
READ
Reset
Value
0y0: SRC0 start address ≠ DST start address
0y1: SRC0 start address = DST start address
0y1: SRC0 DX, DY ≠ SRC1 DX, DY
Read as undefined. Write as zero.
Read Step address until the next line of SRC0 data
Read as undefined. Write as zero.
Horizontal Read Step address of SRC0 data
0y0: SRC0 DX, DY = SRC1 DX, DY
Source image 0
Source image 1
Overwriting to VRAM area
for convenience when the
start address is same
Color
Color
VRAM area
RAM
(16bpp)
(16bpp)
Description
Address
(0xF205_0000) + (0x0038)
TMPA901CM
2010-07-29