TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 502

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.3.2 Specifications of Flags
Note: While the time when the host begins Chirp and the driving time of Chirp-K and Chirp-J depend on the host,
(1) USB_RESET
(2) INT_SETUP
(3) INT_STATUS_NAK
(4) INT_STATUS
(5) INT_EP0
asserting period of the USB_RESET flag is around 1.74 ms to 3.5 ms.
by receiving USB_RESET, the application also needs to return to the Default-State.
recognized for 2.5 s or longer. In High-Speed operation, the flag is asserted when SE0
was recognized for 3 ms or longer, after determining whether USB_RESET or
suspended state. Then, after UDC2 has driven Chirp-K for about 1.5 ms the flag will be
deasserted when either one of the following states was recognized:
interrupt is recognized, the software should read the Setup-Data storage register (8
bytes) to make judgment of request. This interrupt will be deasserted by writing 1 into
the relevant bit (bit 0) of INT register. INT register should be cleared at the point the
interrupt was recognized.
packets while UDC2 is processing the DATA-Stage (before issuing the “Setup_Fin”
command), UDC2 will return “NAK” and asserts this flag to “H”. When this interrupt
is recognized, the software should issue the “Setup_Fin” command from the Command
register to make the STATUS-Stage of UDC2 end. This interrupt will be deasserted by
writing 1 into the relevant bit (bit 1) of INT register. INT register should be cleared at
the point the interrupt was recognized.
interrupt will be deasserted by writing 1 into the relevant bit (bit 2) of INT register.
INT register should be cleared at the point the interrupt was recognized.
received (when the transaction finished normally). This interrupt will be deasserted by
writing 1 into the relevant bit (bit 5) of INT register. INT register should be cleared at
the point the interrupt was recognized.
section discusses those flags.
Asserts “H” while receiving USB_RESET. Since UDC2 returns to the Default-State
In Full-Speed operation, UDC2 asserts this flag when SE0 on the USB bus was
1. Chirp from the host (K-J-K-J-K-J) was recognized.
2. 2 ms or longer has passed without recognizing Chirp from the host (K-J-K-J-K-J).
In Control transfers, asserts “H” after receiving the Setup-Token. When this
In Control transfers, when the host proceeds to the STATUS-Stage and transmits
In Control transfers, asserts “H” after finishing the STATUS-Stage normally. This
In the DATA-Stage of Control transfers, asserts “H” when “ACK” was sent or
The UDC2 core outputs various events on USB as flags when they occur. This
TMPA901CM- 501
TMPA901CM
2010-07-29