TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 415

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.15.3
Note: When using the SPI slave mode without using the FSS pin, be sure to write 1 byte or more of data into the
• Serial clock (SP0CLK)
SSP is idle. For SPI frame format, the serial clock (SP0CLK) is held inactive while the SSP
is idle. SP0CLK is output at the specified bit rate only while data is being transmitted.
(1) Configuring the SSP
(3) Clock ratios
(2) Enabling the SSP
(4) Frame format
SPP Operation
been written into the transmit FIFO or when transmit data is written into the transmit
FIFO after SSP operation has been enabled.
programmed, and is transmitted starting with the MSB.
SSP0CR1under either of the following protocols.. The communication rate need also be
set by programming the prescale register SSP0CPSR and SSP0CR0<SCR>.
the transmit interrupt will be generated. It is possible to use this interrupt to write the
initial transmit data.
The PCLK frequency setting must satisfy the following conditions:
[Master mode]
For SSI and Microwire frame formats, the serial clock (SP0CLK) is held Low while the
[Slave mode]
This SSP supports the following frame formats:
The SSP communication protocol must be configured while the SSP is disabled.
Select master or slave mode by setting the control register SSPOCR0 and
Transmission of data begins when SSP operation is enabled after transmit data has
However, if the transmit FIFO has four entries or less when SSP operation is enabled,
Each frame format is between 4 to 16 bits long depending on the size of data
• SPI
• SSI
• Microwire
transmit FIFO before enabling SSP operation. If SSP operation is enabled while the transmit FIFO is empty,
transfer data cannot be output properly.
f
f
f
f
SP0CLK
SP0CLK
SP0CLK
SP0CLK
(max): f
(min): f
(max): f
(min): f
PCLK
PCLK
PCLK
PCLK
/ (254
/ (254
/ 2
/ 12
TMPA901CM- 414
256)
256)
TMPA901CM
2010-07-29