TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 832

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

No.
4.3
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
4.3.1
Measuring Condition
Loaded capacitance
Internal bus period (
A0-A23 valid to D0-D15 input
SMCOEn fall to D0-D15 input
SMCOEn low level pulse width
A0-A23 valid to SMCOEn fall
SMCOEn rise to D0-D15 hold
SMCOEn high level pulse width
D0-D15 valid to SMCWEn rise
D0-D15 valid to SMCWEn rise (bls=1)
SMCWEn low level width
A0-A23 valid to SMCWEn fall
SMCWEn rise to A0-A23 hold
SMCWEn rise to D0-D15 hold
SMCOEn rise to D0-D15 output
Data byte control to write complete time
AC Electrical Characteristics
All AC specifications shown below are the measurement results under the following conditions
unless specified otherwise.
Connection
Software configuration
Note: The “Equation” column in the table shows the specifications under the conditions DVCCM 1.7 to 1.9 V or
Note: The internal bus cycle is T=10ns minimum value when the guaranteed temperature is 0 to 70 degree.
The internal bus cycle is T=13.3ns minimum value when the guaranteed temperature is -20 to 85 degree.
AC measurement conditions
Basic Bus Cycles
CL ( 25 pF
Read cycle (asynchronous mode)
Write cycle (asynchronous mode)
The letter “T” used in the equations in the table represents the period of internal bus frequency (f
which is one-half of the CPU clock (f
Output level: High
Input level: High
The variables used in the equations in the table are defined as follows:
DVCCM 3.0 to 3.6 V and DVCC1A DVCC1B DVCC1C 1.4 to 1.6 V.
1. DVCC3IO
1. PMCDRV<DRV_MEM1:0>
2. PMCDRV<DRV_MEM1:0> = 0y01 (Half Drive at 3.3 0.3V)
Parameter
T)
Note)
N = Number of t
K = Number of t
0.9
0.7
0.7
DVCCM, Low
DVCCM, Low
WC
RC
SELDVCCM
cycles
cycles
TMPA901CM- 831
Symbol
t
t
OEHW
t
t
t
t
t
t
t
OEW
t
t
OED
t
t
OEO
SBW
CYC
t
AOE
t
SDS
WW
DW
WA
WD
AW
AD
HR
FCLK
0y11 (Full Drive at 1.8 0.1V)
).
0.1
0.3
(N-M)T – 10.0
(K-L-1)T – 5.0
(K-L-1)T – 5.0
(L+1)T – 10.0
(L+1)T – 10.0
(N-M)T – 8.0
(N)T – 15.0
DVCC3IO
MT – 5.0
MT – 8.0
LT – 8.0
LT – 8.0
M = Number of t
L = Number of t
T – 5.0
DVCCM
Min
10
DVCCM
0
2
Equation
WP
Max
CEOE
800
cycles
cycles
100 MHz
N=10
K=10
M=3
10.0
85.0
60.0
62.0
60.0
60.0
52.0
25.0
25.0
52.0
L=6
5.0
2.0
25
22
0
96 MHz
N=10
K=10
M=3
10.4
89.2
62.8
64.9
26.3
23.3
62.9
62.9
54.5
26.3
26.3
54.5
L=6
5.4
2.0
0
TMPA901CM
2010-07-29
48 MHz
N=5
M=1
20.8
89.2
73.3
75.3
15.8
12.8
73.3
73.3
15.8
15.8
15.8
54.5
K=5
L=3
2.0
54
0
HCLK
Unit
)
ns
ns