TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 461

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

b. <abtmod>
c.
d. <abtpri_w0>
e. <abtpri_r1>
f.
Sets the mode of arbiter. Write access is only available when the abt_en bit is set to 0.
If 0 is set to this bit, access rights to the AHB bus will be given in a round-robin fashion
regardless of the values set to each abtpri_* bit. If 1 is set to this bit, access rights to the
AHB bus will be given in accordance with the access priority based on the values set to
each abtpri_* bit.
0y0: Round-robin
0y1: Fixed priority
<abtpri_w1>
Set the priority of DMA accesses for Master Write 1 when the fixed priority mode is
selected. Write access is only available when the abt_en bit is set to 0.
Priority ranges from [0] (highest) to [3] (lowest).
Set the priority of DMA accesses for Master Write 0 when the fixed priority mode is
selected. Write access is only available when the abt_en bit is set to 0.
Priority ranges from [0] (highest) to [3] (lowest).
Set the priority of DMA accesses for Master Read 1 when the fixed priority mode is
selected. Write access is only available when the abt_en bit is set to 0.
Priority ranges from [0] (highest) to [3] (lowest).
<abtpri_r0>
Set the priority of DMA accesses for Master Read 0 when the fixed priority mode is
selected. Write access is only available when the abt_en bit is set to 0.
Priority ranges from [0] (highest) to [3] (lowest).
TMPA901CM- 460
TMPA901CM
2010-07-29