ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 155

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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18.8
8271D–AVR–05/11
Timer/Counter Timing Diagrams
output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 18-8. Timer/Counter Timing Diagram, no Prescaling
Figure 18-9
OCn pin value is the same as the result of a down-counting compare match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the way
up.
Figure 18-8
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
contains timing data for basic Timer/Counter operation. The figure shows the
ATmega48A/PA/88A/PA/168A/PA/328/P
MAX - 1
Figure 18-7
f
OCnxPCPWM
MAX
OCnx has a transition from high to low even though
Figure
=
Table 18-4 on page
----------------- -
N 510
f
18-7. When the OCR2A value is MAX the
clk_I/O
BOTTOM
I/O
161). The actual OC2x
should be replaced by
BOTTOM + 1
155
T2
)

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