ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 273

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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26.2.1
26.2.2
8271D–AVR–05/11
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
Figure 26-1. Addressing the Flash During SPM
Note:
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below.See
a detailed description and mapping of the Fuse Low byte.
Bit
Rd
Bit
Rd
Z - REGISTER
1. The different variables used in
PROGRAM MEMORY
BIT
PAGE
PROGRAM
COUNTER
15
FLB7
7
7
PAGE ADDRESS
WITHIN THE FLASH
ATmega48A/PA/88A/PA/168A/PA/328/P
ZPCMSB
PCMSB
FLB6
6
6
PCPAGE
FLB5
5
5
Figure 27-3
ZPAGEMSB
PAGEMSB
FLB4
PCWORD
4
4
WORD ADDRESS
WITHIN A PAGE
(1)
are listed in
1
FLB3
0
0
3
3
INSTRUCTION WORD
PAGE
Table 28-11 on page
FLB2
2
2
Table 28-5 on page 299
FLB1
LB2
1
1
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
FLB0
302.
LB1
0
0
273
for

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