ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 224

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
22.5.3
22.5.4
22.5.5
8271D–AVR–05/11
Bus Interface Unit
Address Match Unit
Control Unit
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
• TWBR = Value of the TWI Bit Rate Register.
• PrescalerValue = Value of the prescaler, see
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
mode, enabling the MCU to wake up if addressed by a Master.
The Control unit monitors the TWI bus and generates responses corresponding to settings in the
TWI Control Register (TWCR). When an event requiring the attention of the application occurs
on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta-
tus Register (TWSR) is updated with a status code identifying the event. The TWSR only
contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,
the TWSR contains a special status code indicating that no relevant status information is avail-
able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application
software to complete its tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition.
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 29-15 on page 327
SCL frequency
=
---------------------------------------------------------------------------------------- -
16
+
for value of pull-up resistor.
2(TWBR)
CPU Clock frequency
Table 22-7 on page
(
PrescalerValue
245.
)
224