ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 312

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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28.7.15
28.8
8271D–AVR–05/11
Serial Downloading
Parallel Programming Characteristics
For characteristics of the Parallel Programming, see
page
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 28-7. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
330.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
- 0.3V <
ATmega48A/PA/88A/PA/168A/PA/328/P
AV
CC
< V
MOSI
MISO
SCK
ck
ck
CC
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however,
XTAL1
RESET
GND
(1)
AV
CC
”Parallel Programming Characteristics” on
AVCC
VCC
should always be within 1.8 - 5.5V
+1.8 - 5.5V
+1.8 - 5.5V
Table 28-17 on page
(2)
ck
ck
≥ 12MHz
≥ 12MHz
313, the pin
312

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