ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 239

no-image

ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega168A-AU
Manufacturer:
ATMEL
Quantity:
464
Part Number:
ATmega168A-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-AU
Manufacturer:
Microchip Technology
Quantity:
12 280
Part Number:
ATmega168A-AUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-AUR
Manufacturer:
Microchip Technology
Quantity:
420
Part Number:
ATmega168A-CCU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-CCU
Manufacturer:
Microchip Technology
Quantity:
309
Part Number:
ATmega168A-CCUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-CCUR
Manufacturer:
Microchip Technology
Quantity:
469
Part Number:
ATmega168A-MMH
Manufacturer:
Microchip Technology
Quantity:
2 027
Part Number:
ATmega168A-PU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATmega168A-PU
Manufacturer:
ATMEL
Quantity:
4 800
8271D–AVR–05/11
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
The upper seven bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),
otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable
the acknowledgement of the device’s own slave address or the general call address. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in
The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the
Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-
fer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver
transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave
mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives
all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by
transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expect-
ing NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire
Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.
This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial
Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and
the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared
(by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks
running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may
be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these sleep modes.
TWAR
value
TWCR
value
TWINT
TWA6
0
ATmega48A/PA/88A/PA/168A/PA/328/P
TWEA
TWA5
1
TWSTA
TWA4
0
Device’s Own Slave Address
TWSTO
TWA3
0
TWWC
TWA2
0
TWEN
TWA1
1
TWA0
0
Table
TWGCE
TWIE
X
22-5.
239

Related parts for ATmega168A