ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 196

no-image

ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega168A-AU
Manufacturer:
ATMEL
Quantity:
464
Part Number:
ATmega168A-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-AU
Manufacturer:
Microchip Technology
Quantity:
12 280
Part Number:
ATmega168A-AUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-AUR
Manufacturer:
Microchip Technology
Quantity:
420
Part Number:
ATmega168A-CCU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-CCU
Manufacturer:
Microchip Technology
Quantity:
309
Part Number:
ATmega168A-CCUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega168A-CCUR
Manufacturer:
Microchip Technology
Quantity:
469
Part Number:
ATmega168A-MMH
Manufacturer:
Microchip Technology
Quantity:
2 027
Part Number:
ATmega168A-PU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATmega168A-PU
Manufacturer:
ATMEL
Quantity:
4 800
20.9.1
20.10 Examples of Baud Rate Setting
8271D–AVR–05/11
Using MPCMn
setting, but has to be used differently when it is a part of a system utilizing the Multi-processor
Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-
cates if the frame contains data or address information. If the Receiver is set up for frames with
nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When
the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The
ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in
2. The Master MCU sends an address frame, and all slaves receive and read this frame. In
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so,
4. The addressed MCU will receive all data frames until a new address frame is received.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes full-
duplex operation difficult since the Transmitter and Receiver uses the same character size set-
ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRRn settings in
which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the
UCSRnA is set).
the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and
keeps the MPCMn setting.
The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.
the MPCMn bit and waits for a new address frame from master. The process then
repeats from 2.
ATmega48A/PA/88A/PA/168A/PA/328/P
Table
. UBRRn values
196

Related parts for ATmega168A