ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 297

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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28. Memory Programming
28.1
8271D–AVR–05/11
Program And Data Memory Lock Bits
T h e
ATmega88A/88PA/168A/168PA/328/328Pprovides six Lock bits. These can be left unpro-
grammed (“1”) or can be programmed (“0”) to obtain the additional features listed in
The Lock bits can only be erased to “1” with the Chip Erase command.
The ATmega 48A/48PA has no separate Boot Loader section, and the SPM instruction is
enabled for the whole Flash if the SELFPRGEN fuse is programmed (“0”). Otherwise the SPM
instruction is disabled.
Table 28-1.
Notes:
Table 28-2.
Notes:
BLB12
BLB11
BLB02
BLB01
LB2
LB1
LB Mode
Lock Bit Byte
1
2
3
(2)
(2)
(2)
(2)
1. “1” means unprogrammed, “0” means programmed.
2. Only on ATmega88A/88PA/168A/168PA/328/328P.
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
A T m e g a
Memory Lock Bits
Lock Bit Byte
Lock Bit Protection Modes
LB2
1
1
0
ATmega48A/PA/88A/PA/168A/PA/328/P
4 8 A / 4 8 P A
(1)
LB1
1
0
0
Bit No
7
6
5
4
3
2
1
0
Protection Type
No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Boot
Lock bits and Fuse bits are locked in both Serial and Parallel
Programming mode.
p r o v i d e s
(1)(2)
Description
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
Lock bit
t w o
(1)
L o c k
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
b i t s
a n d
Table
(1)
28-2.
t h e
297