ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 234

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Table 22-3.
8271D–AVR–05/11
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x38
0x40
0x48
0x50
0x58
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Arbitration lost in SLA+R or
NOT ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
Status codes for Master Receiver Mode
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-
out losing control over the bus.
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
ATmega48A/PA/88A/PA/168A/PA/328/P
Application Software Response
STA
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
STO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
To TWCR
TWIN
T
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWE
A
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
2-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
234

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