TMP92xy21FG Toshiba, TMP92xy21FG Datasheet
TMP92xy21FG
Specifications of TMP92xy21FG
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TMP92xy21FG Summary of contents
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... TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CH21FG Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Preface ...
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Outline and Device Characteristics The TMP92CH21 is a high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. The TMP92CH21 has a high-performance CPU (900/H1 CPU) and various built-in I/Os. The TMP92CH21FG is housed in a 144-pin ...
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USB (universal serial bus) controller: 1 channel • Compliant with USB ver.1.1 • Full-speed (12 Mbps) (Low-speed is not supported.) • Endpoints spec Endpoint 0: Control 64 bytes* 1-FIFO Endpoint 1: BULK (out) 64 bytes* 2-FIFO Endpoint 2: BULK ...
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... RTC (fs = 32.768 kHz) (25) Operating voltage: • VCC = 3 3.6 V (fc max = 40 MHz) • VCC = 2 3.6 V (fc max = 27 MHz) (26) Package: • 144-pin QFP (LQFP144-P-1616-0.40C) • 144-pin chip form is also available. For details, contact your local Toshiba sales representative. 92CH21-3 TMP92CH21 2009-06-19 ...
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PG0 to PG1 (AN0 to AN1) AN2/MX (PG2) 10-bit AN3/MY/ (PG3) 4-channel ADTRG AD converter AVCC, AVSS VREFH, VREFL Touch (PX, INT4) P96 screen (PY, INT5) P97 I/F (TSI) (TXD0, TXD1) PF0 Serial I/O (RXD0, RXD1) PF1 SIO0 (SCLK0,SCLK1) PF2 ...
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Pin Assignment and Functions The assignment of input/output pins for the TMP92CH21FG, their names and functions are as follows: 2.1 Pin Assignment VREFL 1 VREFH PG0, AN0 PG1, AN1 PG2, AN2 PG3, AN3 ADTRG P96, ...
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PAD Assignment (Chip size 5.98 mm × 6.42 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Pin X Y Name No Point Point −2852 1 2671 VREFL −2852 2 2546 VREFH −2852 3 PG0 2421 −2852 4 2296 PG1 ...
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Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Number of Pin Name I/O Pins I/O Data: Data bus 0 to ...
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Table 2.3.2 Pin Names and Functions (2/5) Number of Pin Name I/O Pins P80 Output Port80: Output port 1 Output Chip select 0: Outputs “low” when address is within specified address area CS 0 P81 Output Port81: Output port Output ...
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Table 2.3.3 Pin Names and Functions (3/5) Number of Pin Name I/O Pins PC0 I/O Port C0: I/O port (Schmitt-input) INT0 1 Input Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge TA1OUT Output 8-bit timer 1 output: ...
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Table 2.3.4 Pin Names and Functions (4/5) Number of Pin Name I/O Pins PJ0 Output Port J0: Output port 1 Output Row address strobe for SDRAM SDRAS Output Data enable for SRAM on pins SRLLB PJ1 Output ...
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Table 2.3.5 Pin Names and Functions (5/5) Number of Pin Name I/O Pins USB-data connecting pin D+, D− 2 I/O Connect pull-up resistor to both pins to avoid through current when USB is not in use. Operation mode: Fix to ...
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Operation This section describes the basic components, functions and operation of the TMP92CH21. 3.1 CPU The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the ...
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Reset Operation When resetting the TMP92CH21, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET At reset, since the clock doubler (PLL) is bypassed ...
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Write Read Figure 3.1.2 TMP92CH21 Reset Timing Chart 92CH21-14 TMP92CH21 2009-06-19 ...
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Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Operation Mode 16-bit external bus starting (MULTI 16 mode) 32-bit external bus starting (MULTI ...
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Memory Map Figure 3.2 memory map of the TMP92CH21. 000000H Internal I/O (8 Kbytes) 000100H 001D00H 002000H Internal RAM (16 Kbytes) 006000H 010000H 3FE000H Boot (Internal MROM) (8 Kbytes) 400000H External memory F00000H Provisional emulator control (64 ...
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Clock Function and Stand-by Function The TMP92CH21 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reduction circuits. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 ...
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The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 ...
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Block Diagram of System Clock (High/low-frequency oscillator) SYSCR0<XTEN > XT1 fs Low-frequency XT2 oscillator f PLL SYSCR0<XEN > Clock doubler (PLL) X1 High-frequency oscillator X2 f OSCH (48 MHz × 16/3 f USB OSCH f SYS f ...
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SFR 7 Bit symbol XEN SYSCR0 (10E0H) Read/Write R/W Reset state 1 Function High- Low- frequency frequency oscillator oscillator (fc) (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation 7 Bit symbol SYSCR1 (10E1H) Read/Write Reset state Function 7 ...
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Bit symbol PROTECT EMCCR0 (10E3H) Read/Write R Reset state 0 Function Protect flag 0: OFF 1: ON EMCCR1 Bit symbol (10E4H) Read/Write Reset state Function Bit symbol EMCCR2 (10E5H) Read/Write Reset state Function Note: When restarting the oscillator from ...
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Bit symbol PLLCR0 (10E8H) Read/Write Reset state Function Select fc clock Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. 7 PLLCR1 Bit symbol PLLON (10E9H) Read/Write R/W Reset state 0 Function ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc ...
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Example 1: Setting the clock Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 EQU 10E0H SYSCR1 EQU 10E1H SYSCR2 EQU 10E2H (SYSCR2 − − SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: ...
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Example 2: Setting the clock Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 EQU 10E0H SYSCR1 EQU 10E1H SYSCR2 EQU 10E2H (SYSCR2 − − SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: ...
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Clock gear controller f is set according to the contents of the clock gear select register FPH SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f reduces power ...
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Clock Doubler (PLL) PLL outputs the f low-speed-frequency oscillator can be used, even though the internal clock is high-frequency. A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed before use. As with an ...
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Example 2: PLL stopping PLLCR0 EQU 10E8H PLLCR1 EQU 10E9H LD (PLLCR0), X0XXXXXXB LD (PLLCR1), 0XXXXXXXB X: Don’t care <FCSEL> <PLLON> PLL output: f PLL System clock f SYS Changes from 40 MHz to 10 MHz ; Changes fc from ...
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Limitations on the use of PLL not possible to execute PLL enable/disable control in the SLOW mode (fs) (writing to PLLCR0 and PLLCR1). PLL should be controlled in the NORMAL mode. 2. When stopping PLL operation during ...
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Change/stop control (OK) PLL use mode (f PLL PLL Stop → Low-frequency oscillator operation mode (fs) → High-frequency oscillator stop − 0 − − − − − − (PLLCR0), 0 − − − − − − ...
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Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (1) ...
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Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Resonator C2 XT2 pin (Setting method) The drive ability of the oscillator is reduced by writing 0 ...
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Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or ...
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Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register and each pin-status is set according ...
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The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode SYSCR2<HALTM1:0> CPU I/O ports TMRA, TMRB SIO AD converter Block WDT I2S, LCDC, SDRAMC, Interrupt controller, USBC, ...
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Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode INTWD INT0 to INT4 (Note 1) INTALM0 to INTALM4 INTTA0 to INTTA3, INTTB0 to INTTB1 INTRX0 to INTRX1, TX0 to TX1 INTTBO0, INTI2S ...
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Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of ...
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STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure ...
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Input Port Name Function During Name Reset OFF 16bit start : OFF 32bit start : OFF P10 to P17 D8 to D15 Boot start : ON 16bit start : ON P20 to P27 D16 ...
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Output Port Name Function During Name Reset D0~D7 D0~D7 P10~P17 D8~D15 OFF D16~D23, P20~P27 KO0~KO7 P30~P37 D24~D31 P40~P47 A0-A7 P50~P57 A8~A15 ON P60~P67 A16~A23 P70 RD P71 , WRLL NDRE OFF P72 , NDWE WRLU P73 EA24 ON P74 EA25 ...
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Output Port Function During Name Name Reset * 1 PA3~PA6 LD8~LD11 PC0 TA1OUT PC1 TA3OUT PC2 TB0OUT0 − PC3 OFF PC6 KO8, LDIV PC7 , LCP1 CSZF PF0 TXD0, TXD1 − PF1 PF2 SCLK0, SCLK1 ON PF7 SDCLK PG2 MX ...
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Interrupts Interrupts are controlled by the CPU Interrupt mask register <IFF2:0> (bits12 the status register) and by the built-in interrupt controller. The TMP92CH21 has a total of 50 interrupts divided into the following five types: Interrupts ...
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Interrupt processing Interrupt specified by micro DMA start vector ? Interrupt vector calue “V” read interrupt request F/F clear General-purpose interrupt PUSH PC processing PUSH SR SR<IFF2:0> ← Level of INTNEST ← INTNEST + 1 PC ← (FFFF00H + V) ...
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General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), ...
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Table 3.4.1 TMP92CH21 Interrupt Vectors and Micro DMA Start Vectors Interrupt Source and Source of Default Type Priority 1 Reset or [SWI0] instruction 2 [SWI1] instruction 3 Illegal instruction or [SWI2] instruction 4 [SWI3] instruction Non- 5 [SWI4] instruction maskable ...
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Interrupt Source and Source of Default Type Priority 51 (Reserved) 52 INTAD: AD conversion end 53 INTTC0: Micro DMA end (Channel 0) 54 INTTC1: Micro DMA end (Channel 1) 55 INTTC2: Micro DMA end (Channel 2) 56 INTTC3: Micro DMA ...
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Micro DMA Processing In addition to general purpose interrupt processing, the TMP92CH21 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level ...
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Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of ...
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Soft start function The TMP92CH21 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing ...
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Detailed description of the transfer mode register Mode DMAMn[4: Destination INC mode (DMADn+) ← (DMASn) DMACn ← DMACn − DMACn = 0 then INTTCn ...
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Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left hand side of the diagram shows the interrupt controller circuit. The right hand side shows the CPU interrupt request signal circuit and the halt ...
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Figure 3.4.3 Block Diagram of Interrupt Controller 92CH21-52 TMP92CH21 2009-06-19 ...
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Interrupt level setting registers Symbol Name Address INT0 & INTE0AD F0H INTAD enable INT1 & INTE12 D0H INT2 enable INT3 & INTE34 D1H INT4 enable INT5 & INTE5I2S EBH INTI2S enable INTTA0 & INTETA01 D4H INTTA1 enable INTTA2 & ...
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Symbol Name Address INTALM4 INTEALM4 E7H enable INTRTC INTERTC E8H enable INTKEY INTEKEY E9H enable INTLCD INTELCD EAH enable INTNDF0 & IN1C INTEND01 ECH INTNDF1 enable INTP0 INTEP0 EEH enable Interrupt request flag − − − ...
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Symbol Name Address 7 INTTC0 ITC1C & INTETC01 F1H INTTC1 R enable 0 INTTC2 ITC3C & INTETC23 F2H INTTC3 R enable 0 INTTC4 ITC5C & INTETC45 F3H INTTC5 R enable 0 INTTC6 & ITC7C INTTC7 INTETC67 F4H R enable 0 ...
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External interrupt control Symbol Name Address I5EDGE Interrupt F6H INT5EDGE input IIMC (Prohibit mode 0: Rising RMW) control 1: Falling *INT0 level enable 0 Edge detect INT 1 “H” level INT Note 1: Disable INT0 request before changing INT0 ...
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SIO receive interrupt control Symbol Name Address SIO F5H Always interrupt SIMC (Prohibit write “0” mode RMW) (Note) control Note: When using the micro DMA transfer end interrupt, always write “1”. INTRX1 level enable 0 Edge detect INTRX1 1 ...
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Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following ...
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Symbol Name Address 7 DMA0 DMA0V start 100H vector DMA1 DMA1V start 101H vector DMA2 DMA2V start 102H vector DMA3 DMA3V start 103H vector DMA4 DMA4V start 104H vector DMA5 DMA5V start 105H vector DMA6 DMA6V start 106H vector DMA7 ...
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Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB ...
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Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute ...
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Function of Ports The TMP92CH21 I/O port pins are shown in Table 3.5.1 and Table 3.5.2. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.5.3 to ...
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with programmable pull-down resistor with pull-up resistor) Number Port Name Pin Name of Pins Port G PG0 to PG1 2 PG2 1 PG3 1 Port J PJ0 1 PJ1 1 PJ2 1 PJ3 1 ...
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Table 3.5.3 I/O Registers and Specifications (1/3) Port Pin Name Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 to P27 Input port Output port D16 to D23 bus KO0 to KO7 Port ...
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Table 3.5.4 I/O Registers and Specifications (2/3) Port Pin Name Port 9 P90 to P94, Input port P96 to P97 P90 to P94 Output port P95 P90 TXD0 output I2SCKO output TXD0 output (Open drain) P91 RXD0 input I2SDO output ...
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Table 3.5.5 I/O Registers and Specifications (3/3) Port Pin Name Specification Port G PG0 to PG3 Input port AN0 to AN3 input PG3 input ADTRG PG2 MX output PG3 MY output Port J PJ0 to PJ7 Output port PJ5 to ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O ...
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P1 Bit symbol P17 (0004H) Read/Write Reset State 7 P1CR Bit symbol P17C (0006H) Read/Write Reset State 0 Function 7 P1FC Bit symbol (0007H) Read/Write Reset State Function 7 P1DR Bit symbol P17D (0081H) Read/Write Reset State 1 Function ...
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Port 2 (P20 to P27) Port 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O ...
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P2 Bit symbol P27 (0008H) Read/Write Reset State 7 P2CR Bit symbol P27C (000AH) Read/Write Reset State 0 Function 7 P2FC Bit symbol (000BH) Read/Write Reset State Note 2 Function 7 P2FC2 Bit symbol P27F2 (0009H) Read/Write Reset State ...
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Port 3 (P30 to P37) Port 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O ...
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P3 Bit symbol P37 (000CH) Read/Write Reset State 7 P3CR Bit symbol P37C (000EH) Read/Write Reset State 0 Function 7 P3FC Bit symbol (000FH) Read/Write Reset State Function 7 P3DR Bit symbol P37D (0083H) Read/Write Reset State 1 Function ...
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Port 4 (P40 to P47) Port 8-bit general-purpose output port. In addition to functioning as a general-purpose output port, port 4 can also function as an address bus (A0 to A7). AM1 ...
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P4 Bit symbol P47 (0010H) Read/Write Reset State 0 7 P4FC Bit symbol P47F (0013H) Read/Write Reset State 0/1 Note 2 Function 7 P4DR Bit symbol P47D (0084H) Read/Write Reset State 1 Function Note 1: Read-modify-write is prohibited for ...
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Port 5 (P50 to P57) Port 8-bit general-purpose output port. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). AM1 AM0 ...
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P5 Bit symbol P57 (0014H) Read/Write Reset State 0 7 P5FC Bit symbol P57F (0017H) Read/Write Reset State 0/1 Note 2 Function 7 P5DR Bit symbol P57D (0085H) Read/Write Reset State 1 Function Note 1: Read-modify-write is prohibited for ...
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Port 6 (P60 to P67) Port 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O ...
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P6 Bit symbol P67 (0018H) Read/Write Reset State 7 P6CR Bit symbol P67C (001AH) Read/Write Reset State 0 Function 7 P6FC Bit symbol P67F (001BH) Read/Write Reset State 0/1 Note 2 Function 7 P6DR Bit symbol P67D (0086H) Read/Write ...
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Port 7 (P70 to P76) Port 7-bit general-purpose I/O port (P70, P73 and P74 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register ...
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P7CR register P7FC register P7 register R/ W Port read data NDR/ B P7CR register P7FC register P7 register Port read data WAIT Selector Figure 3.5.14 Port 7 92CH21-80 TMP92CH21 P75 (R/ , NDR/ ...
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P7 Bit symbol (001CH) Read/Write Reset State 7 P7CR Bit symbol (001EH) Read/Write Reset State Function 0: Input port, WAIT 1:Output port 7 P7FC Bit symbol (001FH) Read/Write Reset State Function Refer to following table 7 P7DR Bit symbol ...
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Port 8 (P80 to P87) Ports are 8-bit output ports. Resetting sets the output latch of P82 to “0” and the output latches of P80 to P81, P83 to P87 to “1”. Port 8 can also ...
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P8 Bit symbol P87 (0020H) Read/Write Reset State 1 7 P8FC Bit symbol P87F (0023H) Read/Write Reset State 0 Function 0: Port 1: CSZE 7 P8FC2 Bit symbol P87F2 (0021H) Read/Write Reset State 0 Function 0: <P87F> 1: SRUUB ...
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Port 9 (P90 to P97) P90 to P94 are 5-bit general-purpose I/O ports. I/O can be set on a bit basis using the control register. Resetting sets P90 to P94 to input port and all bits of output latch ...
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Reset Direction control P9CR write Function control P9FC write S A Output latch Selector B P9 write I2SDO output SCLK0,I2SWS output Selector P9 read (to Port F1) P91RXD0 input (to Port F2) P92SCLK0 input Figure 3.5.19 P91 and P92 (2) ...
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P95 (CLK32KO, LGOE2) Reset Direction control P9CR write Function control P9FC write Output latch P9 write LGOE2 fs P9 read Figure 3.5.21 Port 95 (4) P96 (INT4, PX), P97 (INT5, PY) Reset Function control P9FC write P9 read INT4 ...
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P9 Bit symbol P97 (0024H) Read/Write R Reset State Data from external port 7 P9FC Bit symbol (0026H) Read/Write Reset State Function 7 P9FC Bit symbol P97F (0027H) Read/Write Reset State 0 Function 0: Input port 1: INT5 P92 ...
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Port A (PA0 to PA7) Ports are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports can also keyboard interface, operate a key-on wakeup function. ...
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PA Bit symbol PA7 (0028H) Read/Write Reset State 7 PAFC Bit symbol PA7F (002BH) Read/Write Reset State 0 Function 7 PACR Bit symbol (002AH) Read/Write Reset State Function 7 PADR Bit symbol PA7D (008AH) Read/Write Reset State 1 Function ...
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Port C (PC0 to PC3, PC6 to PC7) PC0 to PC3, PC6 and PC7 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port input port. In addition ...
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PC1 (INT1, TA3OUT), PC2 (INT2, TB0OUT0), PC3 (INT3, TB0OUT1) Reset Direction control PCCR write Function control PCFC write S A Output latch Selector B PC write TA3OUT TB0OUT0 PC read INT1 to INT3 Figure 3.5.27 Port C1, C2, C3 ...
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PC6 (KO8, LDIV) Reset Figure 3.5.28 Port (4) PC7 ( , LCP1) CSZF Reset Direction control PCCR write Function control PCFC write Output latch Selector B PC write LDIV S Selector PC read Direction control PCCR ...
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PC Bit symbol PC7 (0030H) Read/Write R/W Reset State Data from external port (Output latch register is set to “1”) 7 PCCR Bit symbol PC7C (0032H) Read/Write W Reset State 0 Function Refer to following table 7 PCFC Bit ...
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Port F (PF0 to PF2, PF7) Ports are 3-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF2 to be input ports. It also sets all bits ...
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Reset Direction control PFCR write S Output latch PF write Selector PF read PFFC<PF1F> S RXD0 Selector RXD1 Figure 3.5.32 Port F1 Reset Direction control PFCR write S Output latch SCLK0 output SCLK1 output PF write Function control PFFC write ...
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Reset Function control PFFC write S Output latch SDCLK PF write PF read Figure 3.5.34 Port F7 92CH21- PF7 (SDCLK) Selector B TMP92CH21 2009-06-19 ...
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PF Bit symbol PF7 (003CH) Read/Write R/W Reset State 1 7 PFCR Bit symbol (003EH) Read/Write Reset State Function 7 PFFC Bit symbol PF7F (003FH) Read/Write W Reset State 1 Function 0: Output 1: SDCLK PF2 Setting <PF2C> 0 ...
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Port G (PG0 to PG3) PG0 to PG3 are 4-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD ...
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Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output ports. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit I/O ports. In addition to functioning as a ...
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PJ Bit symbol PJ7 (004CH) Read/Write Reset State Data from external port 1 (Output latch register is set 7 PJCR Bit symbol (004EH) Read/Write Reset State Function 7 PJFC Bit symbol PJ7F (004FH) Read/Write Reset State 0 Function 0: ...
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Port K (PK0 to PK3) Port 4-bit output port. Resetting sets the output latch PK to “0”, and PK0 to PK3 pins output “0”. In addition to functioning as an output port, port K also functions ...
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Port L (PL0 to PL7) PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL3 pins output “0”. PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be ...
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PL Bit symbol PL7 (0054H) Read/Write Reset State (Output latch register is cleared to “0”) 7 PLCR Bit symbol PL7C (0056H) Read/Write Reset State 0 Function 7 PLFC Bit symbol PL7F (0057H) Read/Write Reset State 0 Function 7 PLDR ...
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Port M (PM1 to PM2) PM1 and PM2 are 2-bit output ports. Resetting sets the output latch PM to “1”, and PM1 and PM2 pins output “1”. In addition to functioning as a port, port M also functions as ...
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PM Bit symbol (0058H) Read/Write Reset State 7 PMFC Bit symbol (005BH) Read/Write Reset State Function 7 PMDR Bit symbol (0096H) Read/Write Reset State Function Note: Read-modify-write is prohibited for the register PMFC. Port M Register ...
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Memory Controller 3.6.1 Functions The TMP92CH21 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for the 4-block address area (block ...
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B0CSL Bit symbol B0WW2 (0140H) Read/Write Reset State B0CSH Bit symbol B0E (0141H) Read/Write Reset State 0 0 (Note) MAMR0 Bit symbol M0V20 (0142H) Read/Write Reset State 1 MSAR0 Bit symbol M0S23 (0143H) Read/Write Reset State 1 B1CSL Bit ...
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BEXCSH Bit symbol (0159H) Read/Write Reset State BEXCSL Bit symbol BEXWW2 (0158H) Read/Write Reset State PMEMCR Bit symbol (0166H) Read/Write Reset State BROMCR Bit symbol (0167H) Read/Write Reset State Note: Read-modify-write is prohibited for BEXCSH and BEXCSL registers. (2) ...
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Basic Functions and Register Setting This section describes the setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions. (1) Block address area specification The block address area is ...
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Example of register setting To set the block address area 64 Kbytes from address 110000H, set the register as follows. Bit 7 6 Bit symbol M1S23 M1S22 Specified value 0 0 M1S23 to M1S16 bits of the memory start ...
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Connection memory specification Setting the <BnOM1:0> bit of the control register (BnCSH) specifies the memory type that is connected with the block address areas. The interface signal is outputted according to the set memory as follows. <BnOM1: 0> Bit ...
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Operand Start Operand Data Size (bit) Address ...
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Wait control The external bus cycle completes a wait of at least two states (100 MHz). Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in the write cycle and the read cycle. ...
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Recovery (Data hold) cycle control Some memory is defined by AC specification about data hold time by read cycle. Therefore, a data conflict problem may occur. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle ...
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Basic bus timing (a) External read/write cycle (0 waits) SDCLK (20 MHz) CSn A23 SRxxB D31 SRWR SRxxB WRxx D31 to D0 (b) External read/write cycle (1 wait) SDCLK (20 MHz) CSn ...
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External read/write cycle (0 waits at SDCLK (20 MHz) CSn A23 SRxxB D31 SRWR SRxxB WRxx D31 to D0 WAIT (d) External read/write cycle (n waits at SDCLK (20 MHz) CSn A23 ...
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Example of wait input cycle (5 waits) FF0 RES SDCLK CSn RD SRWR 1 2 SDCLK (20 MHz) CSn RD FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT FF1 FF2 FF3 ...
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Connecting external memory Figure 3.6.1 shows an example of how to connect an external 16-bit SRAM and 16-bit NOR flash to the TMP92CH21. TMP92CH21 RD SRLLB SRLUB SRWR [15:0] Not connect ...
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ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CH21 supports ROM ...
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Internal Boot ROM Control This section describes the built-in boot ROM. For the specification of S/W in boot ROM, refer to 3.20 boot ROM sections. (1) BOOT mode BOOT mode is started by following AM1 and AM0 pins condition ...
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Bypassing boot ROM After boot sequence in BOOT mode, an application system program may continue to run without reset asserting. In this case, an external memory which is mapped to address 3FE000H to 3FFFFFH cannot be accessed because the ...
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Cautions (1) Note on timing between If the parasitic capacitance of the (Chip select signal possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause ...
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Note on NAND flash area setting Figure 3.6.5 shows a memory map for a NAND flash and RAM built-in LCD driver. Ssince it is recommended that CS3 area be assigned to the address 000000H to 3FFFFFH, the following explanation ...
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The cautions at the time of the functional change chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control ...
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Timers (TMRA) The TMP92CH21 features 4 built-in 8-bit timers (TMRA0-TMRA3). These timers are paired into two modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • ...
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Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 92CH21-126 TMP92CH21 2009-06-19 ...
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Figure 3.7.2 TMRA23 Block Diagram 92CH21-127 TMP92CH21 2009-06-19 ...
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Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided into 8 by the CPU clock f The prescaler operation can be controlled using TA01RUN<TA01PRUN> in the timer control ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator ...
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Comparator (CP0) The comparator compares the value counter with the value set in a timer register. If they match, the up counter is cleared to “0” and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFR 7 TA01RUN Bit symbol TA0RDE (1100H) Read/Write R/W Reset State 0 Function Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are undefined ...
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TA01MOD Bit symbol TA01M1 (1104H) Read/Write Reset State 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA01 Mode Register TA01M0 PWM01 PWM00 TA1CLK1 R/W ...
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TA23MOD Bit symbol TA23M1 (110CH) Read/Write Reset State 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA23 Mode Register TA23M0 PWM21 PWM20 TA3CLK1 R/W ...
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TA1FFCR Bit symbol (1105H) Read/Write Reset State Read-modify- Function write instruction is prohibited. Note: The values of bits4 TA1FFCR are undefined when read. Figure 3.7.7 TMRA Flip-Flop Control Register TMRA1 Flip-Flop Control Register ...
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TA3FFCR Bit symbol (110DH) Read/Write Reset State Read- Function modify- write instruction is prohibited. Note: The values of bits4 TA3FFCR are undefined when read. Figure 3.7.8 TMRA3 Flip-Flop Control Register TMRA3 Flip-Flop Control Register 6 5 ...
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Symbol Address TA0REG 1102H TA1REG 1103H TA2REG 110AH TA3REG 110BH Note: Read-modify-write instruction is prohibited. TMRA Register − W Undefined − W Undefined − W Undefined − W Undefined Figure 3.7.9 8-Bit Timers Register 92CH21-136 TMP92CH21 ...
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Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. 1. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first ...
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Generating duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4-μs square wave pulse ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter 1 (when ...
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The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator ...
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In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be ...
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Example: To generate 1/4 duty 62.5 kHz pulses ( μs Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be 1/62.5 kHz ...
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PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT ...
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In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match ...
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System clock Clock gear − SYSCR0 SYSCR1 <SYSCK> <GEAR2:0> TAxxMOD<TAxCLK1:0> φT1(x2) − 1(fs) 1024/fs 000(x1) 1024/fc 001(x2) 2048/fc ×8 0(fc) 010(x4) 4096/fc 011(x8) 8192/fc 100(x16) 16384/fc (5) Settings for each mode Table 3.7.5 shows the SFR settings for each mode. ...
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External Memory Extension Function (MMU) By providing 3 local areas, the MMU function allows for the expansion of the program/data area up to 512 Mbytes. The recommended address memory map is shown in Figure 3.8.1 and Figure 3.8.2. However, ...
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Address Memory Map 000000H Internal I/O, RAM COMMON-X (2 Mbytes) 200000H LOCAL-X Bank 0 (2 Mbytes) 400000H LOCAL-Y Bank 0 (2 Mbytes) 600000H COMMON-Y (2 Mbytes) 800000H LOCAL-Z Bank 0 (4 Mbytes) C00000H 64 Mbytes(4 Mbytes × 16) COMMON-Z (4 ...
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TMP92CH21 LOCAL-X CS 128 Mbytes 000000H BANK 0 Internal I/O and RAM 31 Figure 3.8.2 Recommended Memory Map for Maximum Specification (Physical address) LOCAL-Y LOCAL SDCS CS 1 CSZA CSZF 64 Mbytes × 384 Mbytes ...
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Address Memory Map 000000H Internal I/O, RAM COMMON-X (2 Mbytes) 200000H LOCAL-X (2 Mbytes) 3FE000H Internal boot ROM (8 Kbytes) 400000H LOCAL-Y (2 Mbytes) 600000H COMMON-Y (2 Mbytes) 800000H LOCAL-Z Bank 0 (4 Mbytes) C00000H 64 Mbytes (4 Mbytes × ...
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Control Registers There are 12 MMU registers, covering 4 functions (program, data read, data write and LCDC display data), in each of 3 local areas (Local-X, Y and Z), providing easy data access. (Instructions for use) First, set the ...
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Program bank register The bank number used as program memory is set to these registers not possible to change program bank number in the same local area. 7 LOCALPX Bit symbol LXE (01D0H) Read/Write R/W Reset State ...
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LCD Display bank register The bank number used as LCD display memory is set to these registers. Since the bank registers for CPU and LCDC are prepared independently, the bank number for CPU (Program, Read data or Write data) ...
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Read data bank register The bank register number used as read data memory is set to these registers. The following is an example where the read data bank register of LOCAL-X is set to “1”. When “ld wa, (xix)” ...
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Write data bank register The bank number used as write data memory is set to these registers. The following is an example where the data bank register of LOCAL-X is set to “1”. When “ld (xix), wa” instruction is ...
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Setting Example Below is a setting example. No. Used as Main (a) routine Character (b) ROM Sub (c) routine LCD (d) display RAM Stack Internal RAM (e) RAM (a) Main routine (COMMON-Z) Logical Physical No Address Address ← (Same) ...
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Sub routine (Bank 0 in LOCAL-Y) Logical Physical No Address Address 16 org 400000H 000000H 17 ld 4000xxH 0000xxH ...
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Serial Channels The TMP92CH21 includes 2 serial I/O channels. For each channel, either UART mode (asynchronous transmission) or I/O interface mode (synchronous transmission) can be selected. I/O interface mode UART mode In mode 1 and mode 2 a parity ...
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Mode 0 (I/O interface mode) Bit0 1 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 Parity Start Bit0 • Mode 2 (8-bit UART mode) No parity Start Bit0 Parity Start Bit0 • Mode 3 (9-bit ...
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Block Diagrams Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR0CR<BR0CK1:0> BR0CR <BR0S3:0> φT0 φT2 φT8 φT32 BR0CR <BR0ADDE> Baud rate generator f IO SCLK0 I/O interface mode SCLK0 Receive counter (UART ...
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Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR1CR<BR1CK1:0> BR1CR <BR1S3:0> φT0 φT2 φT8 φT32 BR1CR <BR1ADDE> Baud rate generator f IO SCLK1 I/O interface mode SCLK1 Receive counter (UART only ÷ 16) ...
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Operation for Each Circuit (1) SIO Prescaler and prescaler clock select There is a 6-bit prescaler for waking serial clock. The prescaler can be run by selecting the baud rate generator as the waking serial clock. Table 3.9.2 shows ...
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Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is ...
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Integer divider (N divider) For example, when the source clock frequency (f clock is φT2 (f /32), the frequency divider N (BR0CR<BR0S3:0> and C BR0CR<BR0ADDE> the baud rate in UART mode is as follows: * ...
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Table 3.9.3 Selection of Transfer Rate (1) (when baud rate generator is used and BR0CR<BR0ADDE> [MHz] SYS Frequency Divider 9.8304 2 ↑ 4 ↑ 8 ↑ 10 12.2880 5 ↑ A 14.7456 2 ↑ 3 ↑ 6 ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> the basic clock is generated by dividing the output ...
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The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When ...
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Handshake function Use of CTS0 errors can be avoided. The handshake function is enabled or disabled by the SC0MOD<CTSE> setting. When the transmission is halted until the interrupt is generated, and it requests the next data send from the CPU. ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU in order from the least significant bit (LSB). When all the bits are shifted out, the transmission buffer becomes empty and generates ...
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Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. 3. Framing error ...
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Timing generation 1. In UART mode Receiving Mode Center of last bit Interrupt Timing (bit8) Framing Error Timing Center of stop bit Parity Error Timing Center of last bit Overrun Error Timing (bit8) In 9-bit and 8-bit + parity ...
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SFR 7 SC0MOD0 Bit symbol TB8 (1202H) Read/Write Reset State 0 Function Transfer Hand data bit8 shake 0: CTS 1: CTS Figure 3.9.7 Serial Mode Control Register (Channel 0, SC0MOD0 CTSE RXE WU R ...
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SC1MOD0 Bit symbol TB8 (120AH) Read/Write Reset State 0 Function Transfer Hand data bit8 shake 0: CTS 1: CTS Figure 3.9.8 Serial Mode Control Register (Channel 1, SC1MOD0 CTSE RXE WU R Receive ...
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SC0CR Bit symbol RB8 (1201H) Read/Write R Reset State Undefined Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with a bit testing ...
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SC1CR Bit symbol RB8 (1209H) Read/Write R Reset State Undefined Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with a bit testing ...
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BR0CR Bit symbol BR0ADDE (1203H) Read/Write Reset State 0 +(16 − K)/16 Function Always write “0”. division 0: Disable 1: Enable +(16 − K)/16 division enable 0 Disable 1 Enable 7 BR0ADD Bit symbol (1204H) Read/Write Reset State ...
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BR1CR Bit symbol BR1ADDE (120BH) Read/Write Reset State 0 + (16 − K)/16 Function Always write “0”. division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disabled 1 Enabled 7 BR1ADD Bit symbol (120CH) Read/Write ...
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TB7 TB6 TB5 SC0BUF (1200H RB7 RB6 RB5 Note: Prohibit read-modify-write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF) 7 Bit symbol I2S0 SC0MOD1 Read/Write R/W (1205H) Reset State 0 Function ...
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Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes data to the transmission buffer. When all data is output, INTES0<ITX0C> will be set ...
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Receiving In SCLK output mode the synchronous clock is output on the SCLK0 pin and the data is shifted to receiving buffer 1. This is initiated when the receive interrupt flag INTES0<IRX0C> is cleared as the received data is ...
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Transmission and receiving (Full duplex mode) When full duplex mode is used, set the receive interrupt level to 0, and only set the interrupt level (from the transmit interrupt. Ensure that the program which transmits ...
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Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled ...
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Main settings ← X PFCR X X ← − PFFC X X ← − SC0MOD0 0 1 ← − SC0CR 0 1 ← 0 BR0CR 0 0 ← − − − INTES0 Interrupt processing ← SC0CR AND ...
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Protocol 1. Select 9-bit UART mode on the master and slave controllers. 2. Set the SC0MOD0<WU> bit on each slave controller enable data receiving. 3. The master controller transmits data one frame at a time. Each frame ...
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Setting example: To link two slave controllers serially with the master controller using the internal clock f TXD RXD Master • Setting the master controller Main ← − PFCR ← − ...
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Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. Transmission data SIO0 Receive data TMP92CH21 (1) Modulation of the transmission data When the transmit data is 0, the ...
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Data format The data format is fixed as follows: • Data length: 8 bits • Parity bits: none • Stop bits: 1 bit (4) SFR Figure 3.9.27 shows the control register SIRCR. Set SIRCR data while SIO0 is stopped. ...
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Notes 1. Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0<SC1:0> to generate baud rate. Settings other than the above (TA0TRG The pulse width for transmission The IrDA 1.0 specification is defined in Table ...
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Using IrDA 115.2 Kbps with USB When the system uses USB , set f 115.2 Kbps without using the (16 − K)/16 division function. Therefore, only in this case, the following conditions can be used. (Setting condition) • f ...
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SIRCR Bit symbol PLSEL (1207H) Read/Write Reset State 0 Function Select Receive transmit data pulse width 0: “H” pulse 0: 3/16 1: “L” pulse 1: 1/ RXSEL TXEN RXEN SIRWD3 R Transmit Receive ...
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USB Controller 3.10.1 Outline This USB controller (UDC) is designed to support a variety of serial links in the construction of a USB system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed: 12 Mbps (low-speed ...
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System Configuration The USB controller (UDC) consists of the following 3 blocks. 1. 900/H1 CPU I/F (details given in Section 3.10.2, below). 2. UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM and 4 endpoint FIFO ...
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Example USB host USB host USB USB Connector Connector GND VBUS USB cable R8 R9 The above setting is required when using the TMP92CH21’s USB controller Pull- pin ・ In the USB standard, in Full ...
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CPU I/F The 900/H1 CPU I bridge between the 900/H1 CPU and the UDC. Its main functions are as follows:. • INTUSB (interrupt from UDC) generation • A bridge for SFR • USB clock control (48 ...
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USBCR1 Register This register is used to set USB clock enables, transceiver enable etc. 7 bit Symbol TRNS_USE USBCR1 (07F8H) Read/Write R/W Reset State 0 Function • TRNS_USE • WAKEUP • SPEED • USBCLKE WAKEUP R/W ...
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USBINTFRn, MRn Register These SFRs control the INTUSB (only one interrupt to CPU) using the 23 interrupt sources output by the UDC. The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the INTUSB routine, execute operations ...
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Symbol INT_URST_STR USBINTFR1 (07F0H) Read/Write R/W Reset State 0 Function When read 0: Not generate interrupt Note: The above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode cannot be released) *Those 6 interrupts of ...
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Symbol EP1_FULL_A USBINTFR2 (07F1H) Read/Write R/W Reset State 0 Function Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.) 7 bit Symbol USBINTFR3 EP3_FULL_A (07F2H) Read/Write R/W Reset State ...