TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 365

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

LCDCCR0
(0288H)
LCDCCR2
(028AH)
LCDCCR1
(0289H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
by pulse number derived by subtracting common number and <PCPV2:0> from
LCDFFP<FP9:0> (refer to SR mode section).
determines “High width” time as mentioned above. 1 pulse of this time in LCDCCR2
register is equal to 8 times of fsys regardless of LCP0 and LCP1. If “0” is written in
LCDCCR2 register, High level is output during the period that the valid data is output
from LD bus.
called “Delay control 2”. 1 pulse of this set up time in LCDCCR1 register is equal to 8
times of fsys regardless of LCP0 and LCP1. The set up time has offset time; fsys*14 to
16(f
delayed. This offset time changes according to the setting conditions. The cycle of
LCP1 is determined by (the value of LCDSCC register +1) * fsys * 16, thus horizontal
back porch is the time when offset time and set up time are subtracted from the cycle
of LCP1.
Delay control 1 is set by LCDCCR0<PCPV2:0>. Delay of Dummy clock is controlled
Set up time of LLP (horizontal front porch) is set in LCDCCR1<TLDE4:0>. This is
The pulse number of LCP0 in LCDCCR2 means enable time of LLP. This register
(In Mode1, high level is kept during one more LCP0 than valid data.)
LLPSU7
SYS
R/W
7
7
7
0
× 14.5 or more). If “0” is written in LCDCCR1 register, fsys*14 to 16 of time is
LLPSU6
R/W
6
6
6
0
LCD Clock Counter Register 0
LCD Clock Counter Register 1
LCD Clock Counter Register 2
LLPSU5
TFT source driver, LLP_Enable signal: f
R/W
92CH21-363
5
5
5
0
High width time for LLP signal
LLPSU4
TLDE4
R/W
R/W
4
4
4
0
0
Set up time for TFT source driver LLP signal
LLPSU3
TLDE3
LLP_Set-up time: f
R/W
R/W
3
3
3
0
0
(Offset of f
Dummy clock number until valid clock
Pre LCP1 CLK: LCP1 pulse number
LLPSU2
SYS
PCPV2
TLDE2
SYS
R/W
R/W
R/W
2
0
2
2
0
0
× 8
14∼16 pulse)
SYS
of gate driver LCP1
pulse × 8
LLPSU1
PCPV1
TLDE1
R/W
R/W
R/W
1
0
1
1
0
0
TMP92CH21
2009-06-19
LLPSU0
PCPV0
TLDE0
R/W
R/W
R/W
0
0
0
0
0
0