TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 306

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

AN3,
3.11 Analog/Digital Converter
Analog input
ADTRG
AN2 (PG2)
AN1 (PG1)
AN0 (PG0)
converter (AD converter) with 4-channel analog input.
AN3) are shared with the input only port G so they can be used as an input port.
VREFH
VREFL
Note: When IDLE2, IDLE1 or STOP mode is selected, in order to reduce power consumption, the
(PG3)
The TMP92CH21 incorporates a 10-bit successive approximation type analog/digital
Figure 3.11.1 is a block diagram of the AD converter. The 4-channel analog input pins (AN0 to
system may enter a stand-by mode with some timings even though the internal comparator
is still enabled. Therefore be sure to check that AD converter operations are halted before a
HALT instruction is executed.
AD mode control registers 1 and 2
ADMOD1, 2<ADTRGE>
<ADCH2:0><VREFON>
Figure 3.11.1 Block Diagram of AD Converter
Decoder
92CH21-304
Internal data bus
Sample and
<EOCF><ADBF><ITM0><REPEAT><SCAN><ADS>
Channel select
End
hold
AD mode control register 0
Busy
ADMOD0
Interrupt
Comparator
DA converter
AD converter
control circuit
Repeat
Scan
ADREG0H to ADREG3H
ADREG0L to ADREG3L
AD conversion result
Start
ADTRG
INTAD
interrupt
register
TMP92CH21
2009-06-19