TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 110

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

BEXCSH
(0159H)
BEXCSL
(0158H)
PMEMCR
(0166H)
BROMCR
(0167H)
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Note: Read-modify-write is prohibited for BEXCSH and BEXCSL registers.
(2) Operation after reset release
release. The external memory is then accessed as follows
width is set by the control register <BnBUS1:0> .
becomes effective automatically (B2CSH<B2E> is set to “1” on reset).
specification of the bus width of the control register in the block address area 2.
(B2CSH<B2M> is reset to “0”).
address register (MSARn) and the memory address mask register (MAMRn). The
control register (BnCS) is then set.
The start data bus width is determined by the state of AM1/AM0 pins just after reset
AM1/AM0 pins are valid only just after reset release. In other cases, the data bus
On reset, only the control register (B2CSH/B2CSL) of the block address area 2
The data bus width which is specified by AM1/AM0 pins is loaded to the bit for
The block address area 2 is set to 000000H to FFFFFFH address on reset
After reset release, the block address areas are specified by the memory start
Set the enable bit (BnE) of the control register to “1” to enable the setting.
Note: The memory to be used on starting after reset must be either NOR flash or masked ROM.
7
AM1
NAND flash and SDRAM cannot be used.
0
0
1
1
BEXWW2
6
0
AM0
Table 3.6.2 Control Register
0
1
0
1
BEXWW1
W
5
1
92CH21-108
Start with boot (32-bit internal MROM)
Start with 16-bit data bus (Note)
Start with 32-bit data bus (Note)
BEXWW0
OPGE
4
0
0
Don’t use this setting
Start Mode
BEXOM1
OPWR1
3
0
0
BEXOM0
BEXWR2
OPWR0
R/W
2
0
0
0
W
ROMLESS
BEXBUS1
BEXWR1
PR1
W
0/1
1
0
1
1
TMP92CH21
R/W
2009-06-19
BEXBUS0
BEXWR0
VACE
PR0
1/0
0
0
0
0