TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 408

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Bits
Bits
7:1
6:1
0
7
0
3.17.4.5 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR)
3.17.4.6 NAND-Flash Interrupt Mask Register (ND0FIMR and ND1FIMR)
Mnemonic
Mnemonic
INTEN
MRDY
RDY
Figure 3.17.6 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR)
Figure 3.17.7 NAND-Flash Interrupt Mask Register (ND0FIMR and ND1FIMR)
−
−
Interrupt enable
Field Name
Field Name
Mask RDY
interrupt
Ready
−
−
Reserved
Ready (Default: 0)
When NDR/ B signal changes from low (BUSY) to High (
READY) and NDFIMR<MRDY> is “1”, this bit is set to “1”. By writing “1”, this bit is
cleared to 0.
Read:
0: None
1: Change NDR/ B signal from BUSY to READY.
Write:
0: No change
1: Clear to “0”
Interrupt enable (Default: 0)
When <INTEN> and <MRDY> are set “1” and NDFISR<RDY> becomes “1”,
INTNDFC occurs.
0: Disable
1: Enable
Reserved
Mask RDY interrupt (Default: 0)
This bit masks the NDFISR<RDY>. If <MRDY> is “1” and NDR/ B signal changes
from Low to High, NDFISR<RDY> is set to “1”.
0: Disable to set NDFISR<RDY>
1: Enable to set NDFISR<RDY>
INTEN
92CH21-406
R/W
7
7
0
6
6
5
Description
Description
4
4
0
3
3
2
2
1
1
MRDY
RDY
TMP92CH21
R/W
0
0
0
2009-06-19
: Type
: Default
: Type
: Default